New RF with Evaluation
This commit is contained in:
felsabbagh3
4
.gitignore
vendored
4
.gitignore
vendored
@@ -1 +1,3 @@
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./rtl/obj_dir/debug.txt
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./rtl/obj_dir/
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./rtl/.*
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.*
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BIN
rtl/.DS_Store
vendored
BIN
rtl/.DS_Store
vendored
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BIN
rtl/._VX_gpr.v
BIN
rtl/._VX_gpr.v
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@@ -1,4 +1,3 @@
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all: RUNFILE
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@@ -9,5 +8,4 @@ RUNFILE: VERILATOR
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(cd obj_dir && make -j -f VVortex.mk)
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clean:
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rm ./obj_dir/*
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rm ./obj_dir/*
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@@ -46,14 +46,13 @@ module VX_csr_handler (
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end
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end
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reg[11:0] data_read;
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always @(posedge clk) begin
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if(in_mem_is_csr) begin
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csr[in_mem_csr_address] <= in_mem_csr_result[11:0];
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end
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end
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reg[11:0] data_read;
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always @(negedge clk) begin
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data_read <= csr[decode_csr_address];
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end
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@@ -1,5 +1,3 @@
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#define NT 4
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#define NT_M1 (NT-1)
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@@ -97,11 +95,4 @@
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// COLORS
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#define GREEN "\033[32m"
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#define RED "\033[31m"
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#define DEFAULT "\033[39m"
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#define DEFAULT "\033[39m"
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74
rtl/VX_gpr.v
74
rtl/VX_gpr.v
@@ -11,12 +11,40 @@ module VX_gpr (
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output reg[`NT_M1:0][31:0] out_b_reg_data
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);
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logic[`NT_M1:0][31:0] gpr[31:0]; // gpr[register_number][thread_number][data_bits]
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wire write_enable;
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assign write_enable = valid_write_request && ((VX_writeback_inter.wb != 0) && (VX_writeback_inter.rd != 5'h0));
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// USING RAM blocks
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// First RAM
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byte_enabled_simple_dual_port_ram first_ram(
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.we (write_enable),
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.clk (clk),
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.waddr(VX_writeback_inter.rd),
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.raddr(VX_gpr_read.rs1),
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.be (VX_writeback_inter.wb_valid),
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.wdata(VX_writeback_inter.write_data),
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.q (out_a_reg_data)
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);
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// Second RAM block
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byte_enabled_simple_dual_port_ram second_ram(
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.we (write_enable),
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.clk (clk),
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.waddr(VX_writeback_inter.rd),
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.raddr(VX_gpr_read.rs2),
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.be (VX_writeback_inter.wb_valid),
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.wdata(VX_writeback_inter.write_data),
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.q (out_b_reg_data)
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);
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// logic[`NT_M1:0][31:0] gpr[31:0]; // gpr[register_number][thread_number][data_bits]
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// wire write_enable;
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// assign write_enable = valid_write_request && ((VX_writeback_inter.wb != 0) && (VX_writeback_inter.rd != 5'h0));
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// assign read_enable = valid_request;
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// // Using Registers
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@@ -35,44 +63,4 @@ module VX_gpr (
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// end
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// USING RAM blocks
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// First RAM
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integer thread_index_1;
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always_ff@(posedge clk)
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begin
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if (write_enable) begin
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for (thread_index_1 = 0; thread_index_1 <= `NT_M1; thread_index_1 = thread_index_1 + 1) begin
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if (VX_writeback_inter.wb_valid[thread_index_1]) begin
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gpr[VX_writeback_inter.rd][thread_index_1] <= VX_writeback_inter.write_data[thread_index_1];
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end
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end
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end
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end
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always @(negedge clk) begin
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out_a_reg_data <= gpr[VX_gpr_read.rs1];
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end
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// Second RAM
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integer thread_index_2;
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always_ff@(posedge clk)
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begin
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if (write_enable) begin
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for (thread_index_2 = 0; thread_index_2 <= `NT_M1; thread_index_2 = thread_index_2 + 1) begin
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if (VX_writeback_inter.wb_valid[thread_index_2]) begin
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gpr[VX_writeback_inter.rd][thread_index_2] <= VX_writeback_inter.write_data[thread_index_2];
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end
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end
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end
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end
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always @(negedge clk) begin
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out_b_reg_data <= gpr[VX_gpr_read.rs2];
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end
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endmodule
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@@ -47,10 +47,10 @@ module VX_gpr_syn (
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// wire[`NT_M1:0][31:0] jal_data;
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// genvar index;
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// for (index = 0; index <= `NT_M1; index = index + 1) assign jal_data[index] = VX_gpr_jal.curr_PC;
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// for (index = 0; index <= `NT_M1; index = index + 1) assign jal_data[index] = 0;
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// assign out_a_reg_data = VX_gpr_jal.is_jal ? jal_data : temp_a_reg_data[VX_gpr_read.warp_num];
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// assign out_a_reg_data = 0 ? jal_data : temp_a_reg_data[VX_gpr_read.warp_num];
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// assign out_b_reg_data = temp_b_reg_data[VX_gpr_read.warp_num];
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@@ -63,7 +63,7 @@ module VX_gpr_syn (
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// wire curr_warp_zero = VX_gpr_read.warp_num == 0;
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// wire context_zero_valid = (VX_writeback_inter.wb_warp_num == 0);
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// wire real_zero_isclone = VX_gpr_clone.is_clone && (VX_gpr_clone.warp_num == 0);
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// wire real_zero_isclone = 0;
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// wire write_register = (VX_writeback_inter.wb != 2'h0) ? (1'b1) : (1'b0);
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@@ -76,10 +76,10 @@ module VX_gpr_syn (
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// .in_src1 (VX_gpr_read.rs1),
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// .in_src2 (VX_gpr_read.rs2),
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// .in_is_clone (real_zero_isclone),
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// .in_src1_fwd (VX_fwd_rsp.src1_fwd),
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// .in_src1_fwd_data (VX_fwd_rsp.src1_fwd_data),
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// .in_src2_fwd (VX_fwd_rsp.src2_fwd),
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// .in_src2_fwd_data (VX_fwd_rsp.src2_fwd_data),
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// .in_src1_fwd (0),
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// .in_src1_fwd_data (0),
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// .in_src2_fwd (0),
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// .in_src2_fwd_data (0),
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// .in_write_register(write_register),
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// .in_write_data (VX_writeback_inter.write_data),
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// .out_a_reg_data (temp_a_reg_data[0]),
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@@ -93,8 +93,8 @@ module VX_gpr_syn (
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// for (r = 1; r < `NW; r = r + 1) begin
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// wire context_glob_valid = (VX_writeback_inter.wb_warp_num == r);
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// wire curr_warp_glob = VX_gpr_read.warp_num == r;
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// wire real_wspawn = VX_gpr_wspawn.is_wspawn && (VX_gpr_wspawn.which_wspawn == r);
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// wire real_isclone = VX_gpr_clone.is_clone && (VX_gpr_clone.warp_num == r);
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// wire real_wspawn = 0;
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// wire real_isclone = 0;
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// VX_context_slave VX_Context_one(
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// .clk (clk),
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// .in_warp (curr_warp_glob),
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@@ -104,10 +104,10 @@ module VX_gpr_syn (
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// .in_src1 (VX_gpr_read.rs1),
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// .in_src2 (VX_gpr_read.rs2),
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// .in_is_clone (real_isclone),
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// .in_src1_fwd (VX_fwd_rsp.src1_fwd),
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// .in_src1_fwd_data (VX_fwd_rsp.src1_fwd_data),
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// .in_src2_fwd (VX_fwd_rsp.src2_fwd),
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// .in_src2_fwd_data (VX_fwd_rsp.src2_fwd_data),
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// .in_src1_fwd (0),
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// .in_src1_fwd_data (0),
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// .in_src2_fwd (0),
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// .in_src2_fwd_data (0),
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// .in_write_register(write_register),
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// .in_write_data (VX_writeback_inter.write_data),
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// .in_wspawn_regs (w0_t0_registers),
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@@ -149,25 +149,6 @@ module VX_gpr_syn (
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assign out_gpr_stall = 0;
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// // WSPAWN FSM
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// reg[3:0] wspawn_state;
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// VX_gpr_read_inter VX_wspawn_gpr_read();
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// VX_wb_inter VX_wspawn_wb_inter();
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// VX_wspawn_gpr_read.rs1
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// always @(posedge clk) begin
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// if ((in_wspawn) && wspawn_state == 0) begin
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// wspawn_state <= 10;
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// end else if (wspawn_state == 1) begin
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// wspawn_state <= 0;
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// end else if (wspawn_state > 0) begin
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// wspawn_state <= wspawn_state - 1;
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// end
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// end
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// assign out_gpr_stall = ((wspawn_state == 0) && VX_gpr_wspawn.is_wspawn) || (VX_gpr_wspawn.is_wspawn > 1);;
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endmodule
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@@ -1,47 +0,0 @@
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set_global_assignment -name FAMILY "Arria 10"
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set_global_assignment -name TOP_LEVEL_ENTITY Vortex
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:33:29 MAY 12, 2019"
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set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Pro Edition"
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set_global_assignment -name VERILOG_FILE ./Vortex.v
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set_global_assignment -name VERILOG_FILE ./VX_alu.v
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set_global_assignment -name VERILOG_FILE ./VX_context.v
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set_global_assignment -name VERILOG_FILE ./VX_context_slave.v
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set_global_assignment -name VERILOG_FILE ./VX_csr_handler.v
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set_global_assignment -name VERILOG_FILE ./VX_d_e_reg.v
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set_global_assignment -name VERILOG_FILE ./VX_decode.v
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set_global_assignment -name VERILOG_FILE ./VX_define.v
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set_global_assignment -name VERILOG_FILE ./VX_e_m_reg.v
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set_global_assignment -name VERILOG_FILE ./VX_execute.v
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set_global_assignment -name VERILOG_FILE ./VX_f_d_reg.v
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set_global_assignment -name VERILOG_FILE ./VX_fetch.v
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set_global_assignment -name VERILOG_FILE ./VX_forwarding.v
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set_global_assignment -name VERILOG_FILE ./VX_m_w_reg.v
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set_global_assignment -name VERILOG_FILE ./VX_memory.v
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set_global_assignment -name VERILOG_FILE ./VX_register_file.v
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set_global_assignment -name VERILOG_FILE ./VX_register_file_master_slave.v
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set_global_assignment -name VERILOG_FILE ./VX_register_file_slave.v
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set_global_assignment -name VERILOG_FILE ./VX_warp.v
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set_global_assignment -name VERILOG_FILE ./VX_writeback.v
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name DEVICE 10AX115U3F45I2SG
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 4
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
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set_global_assignment -name POWER_AUTO_COMPUTE_TJ ON
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 50000
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set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
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set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
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set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
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set_global_assignment -name SDC_FILE clk_const.sdc
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set_global_assignment -name ALLOW_REGISTER_RETIMING OFF
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set_global_assignment -name REMOVE_DUPLICATE_REGISTERS OFF
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set_global_assignment -name AUTO_ROM_RECOGNITION OFF
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set_global_assignment -name AUTO_RAM_RECOGNITION OFF
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set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT ON
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set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS ON
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set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER OFF
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set_global_assignment -name FLOW_DISABLE_ASSEMBLER ON
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set_instance_assignment -name PARTITION_COLOUR 4288217044 -to Vortex -entity Vortex
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33
rtl/byte_enabled_simple_dual_port_ram.v
Normal file
33
rtl/byte_enabled_simple_dual_port_ram.v
Normal file
@@ -0,0 +1,33 @@
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`include "VX_define.v"
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module byte_enabled_simple_dual_port_ram
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(
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input we, clk,
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input wire[4:0] waddr, raddr,
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input wire[`NT_M1:0] be,
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input wire[`NT_M1:0][31:0] wdata,
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output reg[`NT_M1:0][31:0] q
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);
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// Thread Byte Bit
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logic [`NT_M1:0][3:0][7:0] GPR[31:0];
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always_ff@(posedge clk) begin
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if(we) begin
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integer thread_ind;
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for (thread_ind = 0; thread_ind <= `NT_M1; thread_ind = thread_ind + 1) begin
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if(be[thread_ind]) GPR[waddr][thread_ind][0] <= wdata[thread_ind][7:0];
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if(be[thread_ind]) GPR[waddr][thread_ind][1] <= wdata[thread_ind][15:8];
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if(be[thread_ind]) GPR[waddr][thread_ind][2] <= wdata[thread_ind][23:16];
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if(be[thread_ind]) GPR[waddr][thread_ind][3] <= wdata[thread_ind][31:24];
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end
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end
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end
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always_ff@(negedge clk) begin
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q <= GPR[raddr];
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end
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endmodule
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Load Diff
@@ -1,129 +0,0 @@
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// Verilated -*- C++ -*-
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||||
// DESCRIPTION: Verilator output: Primary design header
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||||
//
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||||
// This header should be included by all source files instantiating the design.
|
||||
// The class here is then constructed to instantiate the design.
|
||||
// See the Verilator manual for examples.
|
||||
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#ifndef _VVX_gpr_syn_H_
|
||||
#define _VVX_gpr_syn_H_
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||||
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#include "verilated.h"
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||||
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||||
class VVX_gpr_syn__Syms;
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||||
|
||||
//----------
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||||
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||||
VL_MODULE(VVX_gpr_syn) {
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public:
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// PORTS
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||||
// The application code writes and reads these signals to
|
||||
// propagate new values into/out from the Verilated model.
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||||
// Begin mtask footprint all:
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VL_IN8(clk,0,0);
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VL_IN8(rs1,4,0);
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VL_IN8(rs2,4,0);
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VL_IN8(warp_num,3,0);
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VL_IN8(rd,4,0);
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VL_IN8(wb,1,0);
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VL_IN8(wb_valid,3,0);
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VL_IN8(wb_warp_num,3,0);
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VL_OUT8(out_gpr_stall,0,0);
|
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VL_INW(write_data,127,0,4);
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VL_OUTW(out_a_reg_data,127,0,4);
|
||||
VL_OUTW(out_b_reg_data,127,0,4);
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||||
|
||||
// LOCAL SIGNALS
|
||||
// Internals; generally not touched by application code
|
||||
// Begin mtask footprint all:
|
||||
VL_SIG8(VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__write_enable,0,0);
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||||
VL_SIG8(VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__write_enable,0,0);
|
||||
VL_SIG8(VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__write_enable,0,0);
|
||||
VL_SIG8(VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__write_enable,0,0);
|
||||
VL_SIG8(VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__write_enable,0,0);
|
||||
VL_SIG8(VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__write_enable,0,0);
|
||||
VL_SIG8(VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__write_enable,0,0);
|
||||
VL_SIG8(VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__write_enable,0,0);
|
||||
VL_SIGW(VX_gpr_wrapper__DOT__temp_a_reg_data,1023,0,32);
|
||||
VL_SIGW(VX_gpr_wrapper__DOT__temp_b_reg_data,1023,0,32);
|
||||
VL_SIGW(VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4);
|
||||
VL_SIGW(VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4);
|
||||
VL_SIGW(VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4);
|
||||
VL_SIGW(VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4);
|
||||
VL_SIGW(VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4);
|
||||
VL_SIGW(VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4);
|
||||
VL_SIGW(VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4);
|
||||
VL_SIGW(VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4);
|
||||
|
||||
// LOCAL VARIABLES
|
||||
// Internals; generally not touched by application code
|
||||
// Begin mtask footprint all:
|
||||
VL_SIG8(__Vclklast__TOP__clk,0,0);
|
||||
VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_gpr__out_b_reg_data,127,0,4);
|
||||
VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_gpr__out_a_reg_data,127,0,4);
|
||||
VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_gpr__out_b_reg_data,127,0,4);
|
||||
VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_gpr__out_a_reg_data,127,0,4);
|
||||
VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_gpr__out_b_reg_data,127,0,4);
|
||||
VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_gpr__out_a_reg_data,127,0,4);
|
||||
VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_gpr__out_b_reg_data,127,0,4);
|
||||
VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_gpr__out_a_reg_data,127,0,4);
|
||||
VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_gpr__out_b_reg_data,127,0,4);
|
||||
VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_gpr__out_a_reg_data,127,0,4);
|
||||
VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__5__KET____DOT__vx_gpr__out_b_reg_data,127,0,4);
|
||||
VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__5__KET____DOT__vx_gpr__out_a_reg_data,127,0,4);
|
||||
VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__6__KET____DOT__vx_gpr__out_b_reg_data,127,0,4);
|
||||
VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__6__KET____DOT__vx_gpr__out_a_reg_data,127,0,4);
|
||||
VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__7__KET____DOT__vx_gpr__out_b_reg_data,127,0,4);
|
||||
VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__7__KET____DOT__vx_gpr__out_a_reg_data,127,0,4);
|
||||
|
||||
// INTERNAL VARIABLES
|
||||
// Internals; generally not touched by application code
|
||||
VVX_gpr_syn__Syms* __VlSymsp; // Symbol table
|
||||
|
||||
// PARAMETERS
|
||||
// Parameters marked /*verilator public*/ for use by application code
|
||||
|
||||
// CONSTRUCTORS
|
||||
private:
|
||||
VL_UNCOPYABLE(VVX_gpr_syn); ///< Copying not allowed
|
||||
public:
|
||||
/// Construct the model; called by application code
|
||||
/// The special name may be used to make a wrapper with a
|
||||
/// single model invisible with respect to DPI scope names.
|
||||
VVX_gpr_syn(const char* name="TOP");
|
||||
/// Destroy the model; called (often implicitly) by application code
|
||||
~VVX_gpr_syn();
|
||||
|
||||
// API METHODS
|
||||
/// Evaluate the model. Application must call when inputs change.
|
||||
void eval();
|
||||
/// Simulation complete, run final blocks. Application must call on completion.
|
||||
void final();
|
||||
|
||||
// INTERNAL METHODS
|
||||
private:
|
||||
static void _eval_initial_loop(VVX_gpr_syn__Syms* __restrict vlSymsp);
|
||||
public:
|
||||
void __Vconfigure(VVX_gpr_syn__Syms* symsp, bool first);
|
||||
private:
|
||||
static QData _change_request(VVX_gpr_syn__Syms* __restrict vlSymsp);
|
||||
public:
|
||||
static void _combo__TOP__4(VVX_gpr_syn__Syms* __restrict vlSymsp);
|
||||
private:
|
||||
void _ctor_var_reset() VL_ATTR_COLD;
|
||||
public:
|
||||
static void _eval(VVX_gpr_syn__Syms* __restrict vlSymsp);
|
||||
private:
|
||||
#ifdef VL_DEBUG
|
||||
void _eval_debug_assertions();
|
||||
#endif // VL_DEBUG
|
||||
public:
|
||||
static void _eval_initial(VVX_gpr_syn__Syms* __restrict vlSymsp) VL_ATTR_COLD;
|
||||
static void _eval_settle(VVX_gpr_syn__Syms* __restrict vlSymsp) VL_ATTR_COLD;
|
||||
static void _initial__TOP__1(VVX_gpr_syn__Syms* __restrict vlSymsp) VL_ATTR_COLD;
|
||||
static void _sequent__TOP__2(VVX_gpr_syn__Syms* __restrict vlSymsp);
|
||||
static void _settle__TOP__3(VVX_gpr_syn__Syms* __restrict vlSymsp) VL_ATTR_COLD;
|
||||
} VL_ATTR_ALIGNED(128);
|
||||
|
||||
#endif // guard
|
||||
@@ -1,53 +0,0 @@
|
||||
# Verilated -*- Makefile -*-
|
||||
# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
|
||||
#
|
||||
# Execute this makefile from the object directory:
|
||||
# make -f VVX_gpr_syn.mk
|
||||
|
||||
default: VVX_gpr_syn__ALL.a
|
||||
|
||||
### Constants...
|
||||
# Perl executable (from $PERL)
|
||||
PERL = perl
|
||||
# Path to Verilator kit (from $VERILATOR_ROOT)
|
||||
VERILATOR_ROOT = /usr/local/share/verilator
|
||||
# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
|
||||
SYSTEMC_INCLUDE ?=
|
||||
# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
|
||||
SYSTEMC_LIBDIR ?=
|
||||
|
||||
### Switches...
|
||||
# SystemC output mode? 0/1 (from --sc)
|
||||
VM_SC = 0
|
||||
# Legacy or SystemC output mode? 0/1 (from --sc)
|
||||
VM_SP_OR_SC = $(VM_SC)
|
||||
# Deprecated
|
||||
VM_PCLI = 1
|
||||
# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH)
|
||||
VM_SC_TARGET_ARCH = linux
|
||||
|
||||
### Vars...
|
||||
# Design prefix (from --prefix)
|
||||
VM_PREFIX = VVX_gpr_syn
|
||||
# Module prefix (from --prefix)
|
||||
VM_MODPREFIX = VVX_gpr_syn
|
||||
# User CFLAGS (from -CFLAGS on Verilator command line)
|
||||
VM_USER_CFLAGS = \
|
||||
|
||||
# User LDLIBS (from -LDFLAGS on Verilator command line)
|
||||
VM_USER_LDLIBS = \
|
||||
|
||||
# User .cpp files (from .cpp's on Verilator command line)
|
||||
VM_USER_CLASSES = \
|
||||
|
||||
# User .cpp directories (from .cpp's on Verilator command line)
|
||||
VM_USER_DIR = \
|
||||
|
||||
|
||||
### Default rules...
|
||||
# Include list of all generated classes
|
||||
include VVX_gpr_syn_classes.mk
|
||||
# Include global rules
|
||||
include $(VERILATOR_ROOT)/include/verilated.mk
|
||||
|
||||
# Verilated -*- Makefile -*-
|
||||
@@ -1,19 +0,0 @@
|
||||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Symbol table implementation internals
|
||||
|
||||
#include "VVX_gpr_syn__Syms.h"
|
||||
#include "VVX_gpr_syn.h"
|
||||
|
||||
// FUNCTIONS
|
||||
VVX_gpr_syn__Syms::VVX_gpr_syn__Syms(VVX_gpr_syn* topp, const char* namep)
|
||||
// Setup locals
|
||||
: __Vm_namep(namep)
|
||||
, __Vm_didInit(false)
|
||||
// Setup submodule names
|
||||
{
|
||||
// Pointer to top level
|
||||
TOPp = topp;
|
||||
// Setup each module's pointers to their submodules
|
||||
// Setup each module's pointer back to symbol table (for public functions)
|
||||
TOPp->__Vconfigure(this, true);
|
||||
}
|
||||
@@ -1,35 +0,0 @@
|
||||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Symbol table internal header
|
||||
//
|
||||
// Internal details; most calling programs do not need this header,
|
||||
// unless using verilator public meta comments.
|
||||
|
||||
#ifndef _VVX_gpr_syn__Syms_H_
|
||||
#define _VVX_gpr_syn__Syms_H_
|
||||
|
||||
#include "verilated.h"
|
||||
|
||||
// INCLUDE MODULE CLASSES
|
||||
#include "VVX_gpr_syn.h"
|
||||
|
||||
// SYMS CLASS
|
||||
class VVX_gpr_syn__Syms : public VerilatedSyms {
|
||||
public:
|
||||
|
||||
// LOCAL STATE
|
||||
const char* __Vm_namep;
|
||||
bool __Vm_didInit;
|
||||
|
||||
// SUBCELL STATE
|
||||
VVX_gpr_syn* TOPp;
|
||||
|
||||
// CREATORS
|
||||
VVX_gpr_syn__Syms(VVX_gpr_syn* topp, const char* namep);
|
||||
~VVX_gpr_syn__Syms() {}
|
||||
|
||||
// METHODS
|
||||
inline const char* name() { return __Vm_namep; }
|
||||
|
||||
} VL_ATTR_ALIGNED(64);
|
||||
|
||||
#endif // guard
|
||||
@@ -1 +0,0 @@
|
||||
obj_dir/VVX_gpr_syn.cpp obj_dir/VVX_gpr_syn.h obj_dir/VVX_gpr_syn.mk obj_dir/VVX_gpr_syn__Syms.cpp obj_dir/VVX_gpr_syn__Syms.h obj_dir/VVX_gpr_syn__ver.d obj_dir/VVX_gpr_syn_classes.mk : /usr/local/bin/verilator_bin /usr/local/bin/verilator_bin VX_define.v VX_gpr.v VX_gpr_syn.v interfaces/../VX_define.v interfaces/VX_gpr_read_inter.v interfaces/VX_wb_inter.v
|
||||
@@ -1,17 +0,0 @@
|
||||
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
|
||||
C "VX_gpr_syn.v -cc -Iinterfaces"
|
||||
S 6746612 12892413243 1567548409 0 1567548409 0 "/usr/local/bin/verilator_bin"
|
||||
S 1676 1565244 1567474434 0 1567474434 0 "VX_define.v"
|
||||
S 1179 894272 1568146678 0 1568146678 0 "VX_gpr.v"
|
||||
S 5776 894945 1568156400 0 1568156400 0 "VX_gpr_syn.v"
|
||||
S 1676 1565244 1567474434 0 1567474434 0 "interfaces/../VX_define.v"
|
||||
S 193 894834 1568154198 0 1568154198 0 "interfaces/VX_gpr_read_inter.v"
|
||||
S 273 894835 1568154164 0 1568154164 0 "interfaces/VX_wb_inter.v"
|
||||
T 103876 895616 1568156400 0 1568156400 0 "obj_dir/VVX_gpr_syn.cpp"
|
||||
T 6427 894948 1568156400 0 1568156400 0 "obj_dir/VVX_gpr_syn.h"
|
||||
T 1458 895150 1568156400 0 1568156400 0 "obj_dir/VVX_gpr_syn.mk"
|
||||
T 550 894947 1568156400 0 1568156400 0 "obj_dir/VVX_gpr_syn__Syms.cpp"
|
||||
T 789 894946 1568156400 0 1568156400 0 "obj_dir/VVX_gpr_syn__Syms.h"
|
||||
T 363 895151 1568156400 0 1568156400 0 "obj_dir/VVX_gpr_syn__ver.d"
|
||||
T 0 0 1568156400 0 1568156400 0 "obj_dir/VVX_gpr_syn__verFiles.dat"
|
||||
T 1257 894949 1568156400 0 1568156400 0 "obj_dir/VVX_gpr_syn_classes.mk"
|
||||
@@ -1,40 +0,0 @@
|
||||
# Verilated -*- Makefile -*-
|
||||
# DESCRIPTION: Verilator output: Make include file with class lists
|
||||
#
|
||||
# This file lists generated Verilated files, for including in higher level makefiles.
|
||||
# See VVX_gpr_syn.mk for the caller.
|
||||
|
||||
### Switches...
|
||||
# Coverage output mode? 0/1 (from --coverage)
|
||||
VM_COVERAGE = 0
|
||||
# Threaded output mode? 0/1/N threads (from --threads)
|
||||
VM_THREADS = 0
|
||||
# Tracing output mode? 0/1 (from --trace)
|
||||
VM_TRACE = 0
|
||||
# Tracing threadeds output mode? 0/1 (from --trace-fst-thread)
|
||||
VM_TRACE_THREADED = 0
|
||||
|
||||
### Object file lists...
|
||||
# Generated module classes, fast-path, compile with highest optimization
|
||||
VM_CLASSES_FAST += \
|
||||
VVX_gpr_syn \
|
||||
|
||||
# Generated module classes, non-fast-path, compile with low/medium optimization
|
||||
VM_CLASSES_SLOW += \
|
||||
|
||||
# Generated support classes, fast-path, compile with highest optimization
|
||||
VM_SUPPORT_FAST += \
|
||||
|
||||
# Generated support classes, non-fast-path, compile with low/medium optimization
|
||||
VM_SUPPORT_SLOW += \
|
||||
VVX_gpr_syn__Syms \
|
||||
|
||||
# Global classes, need linked once per executable, fast-path, compile with highest optimization
|
||||
VM_GLOBAL_FAST += \
|
||||
verilated \
|
||||
|
||||
# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization
|
||||
VM_GLOBAL_SLOW += \
|
||||
|
||||
|
||||
# Verilated -*- Makefile -*-
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
@@ -178,14 +178,24 @@ VL_MODULE(VVortex) {
|
||||
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__cycle,63,0);
|
||||
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__instret,63,0);
|
||||
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__in_valid[4],0,0);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4);
|
||||
};
|
||||
struct {
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4);
|
||||
};
|
||||
|
||||
// LOCAL VARIABLES
|
||||
@@ -206,22 +216,22 @@ VL_MODULE(VVortex) {
|
||||
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT____Vlvbound1,11,0);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT____Vcellout__vx_grp_wrapper__out_b_reg_data,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT____Vcellout__vx_grp_wrapper__out_a_reg_data,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_gpr__out_b_reg_data,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_gpr__out_a_reg_data,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_gpr__out_b_reg_data,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_gpr__out_a_reg_data,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_gpr__out_b_reg_data,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_gpr__out_a_reg_data,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_gpr__out_b_reg_data,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_gpr__out_a_reg_data,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__4__KET____DOT__vx_gpr__out_b_reg_data,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__4__KET____DOT__vx_gpr__out_a_reg_data,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__5__KET____DOT__vx_gpr__out_b_reg_data,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__5__KET____DOT__vx_gpr__out_a_reg_data,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__6__KET____DOT__vx_gpr__out_b_reg_data,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__6__KET____DOT__vx_gpr__out_a_reg_data,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__vx_gpr__out_b_reg_data,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__vx_gpr__out_a_reg_data,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_d_e_reg__DOT____Vcellinp__d_e_reg__in,489,0,16);
|
||||
VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result,31,0);
|
||||
|
||||
Binary file not shown.
Binary file not shown.
@@ -1 +1 @@
|
||||
obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex_VX_branch_response_inter.cpp obj_dir/VVortex_VX_branch_response_inter.h obj_dir/VVortex_VX_dcache_request_inter.cpp obj_dir/VVortex_VX_dcache_request_inter.h obj_dir/VVortex_VX_dcache_response_inter.cpp obj_dir/VVortex_VX_dcache_response_inter.h obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp obj_dir/VVortex_VX_frE_to_bckE_req_inter.h obj_dir/VVortex_VX_inst_mem_wb_inter.cpp obj_dir/VVortex_VX_inst_mem_wb_inter.h obj_dir/VVortex_VX_inst_meta_inter.cpp obj_dir/VVortex_VX_inst_meta_inter.h obj_dir/VVortex_VX_mem_req_inter.cpp obj_dir/VVortex_VX_mem_req_inter.h obj_dir/VVortex_VX_warp_ctl_inter.cpp obj_dir/VVortex_VX_warp_ctl_inter.h obj_dir/VVortex_VX_wb_inter.cpp obj_dir/VVortex_VX_wb_inter.h obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/bin/verilator_bin /usr/local/bin/verilator_bin VX_alu.v VX_back_end.v VX_csr_handler.v VX_decode.v VX_define.v VX_execute.v VX_fetch.v VX_forwarding.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_memory.v VX_warp.v VX_writeback.v Vortex.v interfaces//../VX_define.v interfaces//VX_branch_response_inter.v interfaces//VX_csr_write_request_inter.v interfaces//VX_dcache_request_inter.v interfaces//VX_dcache_response_inter.v interfaces//VX_forward_exe_inter.v interfaces//VX_forward_mem_inter.v interfaces//VX_forward_reqeust_inter.v interfaces//VX_forward_response_inter.v interfaces//VX_forward_wb_inter.v interfaces//VX_frE_to_bckE_req_inter.v interfaces//VX_gpr_clone_inter.v interfaces//VX_gpr_jal_inter.v interfaces//VX_gpr_read_inter.v interfaces//VX_gpr_wspawn_inter.v interfaces//VX_icache_request_inter.v interfaces//VX_icache_response_inter.v interfaces//VX_inst_mem_wb_inter.v interfaces//VX_inst_meta_inter.v interfaces//VX_jal_response_inter.v interfaces//VX_mem_req_inter.v interfaces//VX_mw_wb_inter.v interfaces//VX_warp_ctl_inter.v interfaces//VX_wb_inter.v pipe_regs//VX_d_e_reg.v pipe_regs//VX_e_m_reg.v pipe_regs//VX_f_d_reg.v pipe_regs//VX_m_w_reg.v
|
||||
obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex_VX_branch_response_inter.cpp obj_dir/VVortex_VX_branch_response_inter.h obj_dir/VVortex_VX_dcache_request_inter.cpp obj_dir/VVortex_VX_dcache_request_inter.h obj_dir/VVortex_VX_dcache_response_inter.cpp obj_dir/VVortex_VX_dcache_response_inter.h obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp obj_dir/VVortex_VX_frE_to_bckE_req_inter.h obj_dir/VVortex_VX_inst_mem_wb_inter.cpp obj_dir/VVortex_VX_inst_mem_wb_inter.h obj_dir/VVortex_VX_inst_meta_inter.cpp obj_dir/VVortex_VX_inst_meta_inter.h obj_dir/VVortex_VX_mem_req_inter.cpp obj_dir/VVortex_VX_mem_req_inter.h obj_dir/VVortex_VX_warp_ctl_inter.cpp obj_dir/VVortex_VX_warp_ctl_inter.h obj_dir/VVortex_VX_wb_inter.cpp obj_dir/VVortex_VX_wb_inter.h obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/bin/verilator_bin /usr/local/bin/verilator_bin VX_alu.v VX_back_end.v VX_csr_handler.v VX_decode.v VX_define.v VX_execute.v VX_fetch.v VX_forwarding.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_memory.v VX_warp.v VX_writeback.v Vortex.v byte_enabled_simple_dual_port_ram.v interfaces//../VX_define.v interfaces//VX_branch_response_inter.v interfaces//VX_csr_write_request_inter.v interfaces//VX_dcache_request_inter.v interfaces//VX_dcache_response_inter.v interfaces//VX_forward_exe_inter.v interfaces//VX_forward_mem_inter.v interfaces//VX_forward_reqeust_inter.v interfaces//VX_forward_response_inter.v interfaces//VX_forward_wb_inter.v interfaces//VX_frE_to_bckE_req_inter.v interfaces//VX_gpr_clone_inter.v interfaces//VX_gpr_jal_inter.v interfaces//VX_gpr_read_inter.v interfaces//VX_gpr_wspawn_inter.v interfaces//VX_icache_request_inter.v interfaces//VX_icache_response_inter.v interfaces//VX_inst_mem_wb_inter.v interfaces//VX_inst_meta_inter.v interfaces//VX_jal_response_inter.v interfaces//VX_mem_req_inter.v interfaces//VX_mw_wb_inter.v interfaces//VX_warp_ctl_inter.v interfaces//VX_wb_inter.v pipe_regs//VX_d_e_reg.v pipe_regs//VX_e_m_reg.v pipe_regs//VX_f_d_reg.v pipe_regs//VX_m_w_reg.v
|
||||
|
||||
@@ -1,73 +1,74 @@
|
||||
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
|
||||
C "--compiler gcc -Wall -cc Vortex.v -I. -Iinterfaces/ -Ipipe_regs/ --exe test_bench.cpp -CFLAGS -std=c++11 -O3"
|
||||
S 6746612 12892413243 1567548409 0 1567548409 0 "/usr/local/bin/verilator_bin"
|
||||
S 2785 1565236 1567474434 0 1567474434 0 "VX_alu.v"
|
||||
S 2767 1703128 1567984522 0 1567984522 0 "VX_back_end.v"
|
||||
S 1837 1768199 1567984564 0 1567984564 0 "VX_csr_handler.v"
|
||||
S 12015 891625 1568083962 0 1568083962 0 "VX_decode.v"
|
||||
S 1676 1565244 1567474434 0 1567474434 0 "VX_define.v"
|
||||
S 3835 891130 1568052328 0 1568052328 0 "VX_execute.v"
|
||||
S 5000 892191 1568138876 0 1568138876 0 "VX_fetch.v"
|
||||
S 6148 1701713 1567982096 0 1567982096 0 "VX_forwarding.v"
|
||||
S 2701 891626 1568084006 0 1568084006 0 "VX_front_end.v"
|
||||
S 399 1565278 1567537322 0 1567537322 0 "VX_generic_register.v"
|
||||
S 2099 895597 1568160868 0 1568160868 0 "VX_gpr.v"
|
||||
S 5323 894943 1568156252 0 1568156252 0 "VX_gpr_wrapper.v"
|
||||
S 2584 1768087 1567983338 0 1567983338 0 "VX_memory.v"
|
||||
S 1903 893490 1568138384 0 1568138384 0 "VX_warp.v"
|
||||
S 1597 1704649 1567981924 0 1567981924 0 "VX_writeback.v"
|
||||
S 4392 1703129 1567985238 0 1567985238 0 "Vortex.v"
|
||||
S 1676 1565244 1567474434 0 1567474434 0 "interfaces//../VX_define.v"
|
||||
S 227 894833 1568155500 0 1568155500 0 "interfaces//VX_branch_response_inter.v"
|
||||
S 212 894856 1568154236 0 1568154236 0 "interfaces//VX_csr_write_request_inter.v"
|
||||
S 373 894855 1568154234 0 1568154234 0 "interfaces//VX_dcache_request_inter.v"
|
||||
S 186 894854 1568154230 0 1568154230 0 "interfaces//VX_dcache_response_inter.v"
|
||||
S 282 894852 1568154224 0 1568154224 0 "interfaces//VX_forward_exe_inter.v"
|
||||
S 327 894851 1568154222 0 1568154222 0 "interfaces//VX_forward_mem_inter.v"
|
||||
S 204 894850 1568154218 0 1568154218 0 "interfaces//VX_forward_reqeust_inter.v"
|
||||
S 273 894849 1568154216 0 1568154216 0 "interfaces//VX_forward_response_inter.v"
|
||||
S 313 894848 1568154210 0 1568154210 0 "interfaces//VX_forward_wb_inter.v"
|
||||
S 833 894847 1568154206 0 1568154206 0 "interfaces//VX_frE_to_bckE_req_inter.v"
|
||||
S 253 894846 1568154204 0 1568154204 0 "interfaces//VX_gpr_clone_inter.v"
|
||||
S 173 894845 1568154200 0 1568154200 0 "interfaces//VX_gpr_jal_inter.v"
|
||||
S 193 894834 1568154198 0 1568154198 0 "interfaces//VX_gpr_read_inter.v"
|
||||
S 293 894844 1568154194 0 1568154194 0 "interfaces//VX_gpr_wspawn_inter.v"
|
||||
S 159 894843 1568154192 0 1568154192 0 "interfaces//VX_icache_request_inter.v"
|
||||
S 194 894842 1568154188 0 1568154188 0 "interfaces//VX_icache_response_inter.v"
|
||||
S 366 894841 1568154186 0 1568154186 0 "interfaces//VX_inst_mem_wb_inter.v"
|
||||
S 237 894840 1568154182 0 1568154182 0 "interfaces//VX_inst_meta_inter.v"
|
||||
S 205 894839 1568154180 0 1568154180 0 "interfaces//VX_jal_response_inter.v"
|
||||
S 557 894838 1568154176 0 1568154176 0 "interfaces//VX_mem_req_inter.v"
|
||||
S 348 894837 1568154174 0 1568154174 0 "interfaces//VX_mw_wb_inter.v"
|
||||
S 297 894836 1568154170 0 1568154170 0 "interfaces//VX_warp_ctl_inter.v"
|
||||
S 273 894835 1568154164 0 1568154164 0 "interfaces//VX_wb_inter.v"
|
||||
T 768547 894861 1568160870 0 1568160870 0 "obj_dir/VVortex.cpp"
|
||||
T 22072 894859 1568160870 0 1568160870 0 "obj_dir/VVortex.h"
|
||||
T 1791 894923 1568160870 0 1568160870 0 "obj_dir/VVortex.mk"
|
||||
T 914 894911 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_branch_response_inter.cpp"
|
||||
T 1029 894910 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_branch_response_inter.h"
|
||||
T 1210 894907 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_dcache_request_inter.cpp"
|
||||
T 1135 894906 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_dcache_request_inter.h"
|
||||
T 988 894905 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_dcache_response_inter.cpp"
|
||||
T 1045 894904 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_dcache_response_inter.h"
|
||||
T 1059 894909 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp"
|
||||
T 1142 894908 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.h"
|
||||
T 884 894919 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.cpp"
|
||||
T 1008 894918 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.h"
|
||||
T 865 894915 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_inst_meta_inter.cpp"
|
||||
T 987 894914 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_inst_meta_inter.h"
|
||||
T 885 894917 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_mem_req_inter.cpp"
|
||||
T 1005 894916 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_mem_req_inter.h"
|
||||
T 902 894913 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_warp_ctl_inter.cpp"
|
||||
T 1017 894912 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_warp_ctl_inter.h"
|
||||
T 825 894921 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_wb_inter.cpp"
|
||||
T 954 894920 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_wb_inter.h"
|
||||
T 3499 894858 1568160870 0 1568160870 0 "obj_dir/VVortex__Syms.cpp"
|
||||
T 1855 894857 1568160870 0 1568160870 0 "obj_dir/VVortex__Syms.h"
|
||||
T 2077 894924 1568160870 0 1568160870 0 "obj_dir/VVortex__ver.d"
|
||||
T 0 0 1568160870 0 1568160870 0 "obj_dir/VVortex__verFiles.dat"
|
||||
T 1530 894922 1568160870 0 1568160870 0 "obj_dir/VVortex_classes.mk"
|
||||
S 1884 891629 1568084068 0 1568084068 0 "pipe_regs//VX_d_e_reg.v"
|
||||
S 1538 1573254 1567973402 0 1567973402 0 "pipe_regs//VX_e_m_reg.v"
|
||||
S 751 891628 1568084040 0 1568084040 0 "pipe_regs//VX_f_d_reg.v"
|
||||
S 688 1573273 1567972184 0 1567972184 0 "pipe_regs//VX_m_w_reg.v"
|
||||
S 2785 897406 1568177864 0 1568177864 0 "VX_alu.v"
|
||||
S 2767 897407 1568177864 0 1568177864 0 "VX_back_end.v"
|
||||
S 1836 897410 1568177864 0 1568177864 0 "VX_csr_handler.v"
|
||||
S 12015 897411 1568177864 0 1568177864 0 "VX_decode.v"
|
||||
S 1676 897412 1568177866 0 1568177866 0 "VX_define.v"
|
||||
S 3835 897413 1568177866 0 1568177866 0 "VX_execute.v"
|
||||
S 5000 897414 1568177866 0 1568177866 0 "VX_fetch.v"
|
||||
S 6148 897415 1568177866 0 1568177866 0 "VX_forwarding.v"
|
||||
S 2701 897416 1568177866 0 1568177866 0 "VX_front_end.v"
|
||||
S 399 897417 1568177866 0 1568177866 0 "VX_generic_register.v"
|
||||
S 1835 897418 1568177866 0 1568177866 0 "VX_gpr.v"
|
||||
S 5323 897420 1568177866 0 1568177866 0 "VX_gpr_wrapper.v"
|
||||
S 2584 897421 1568177866 0 1568177866 0 "VX_memory.v"
|
||||
S 1903 897425 1568177866 0 1568177866 0 "VX_warp.v"
|
||||
S 1597 897426 1568177868 0 1568177868 0 "VX_writeback.v"
|
||||
S 4392 897427 1568177868 0 1568177868 0 "Vortex.v"
|
||||
S 821 897428 1568177868 0 1568177868 0 "byte_enabled_simple_dual_port_ram.v"
|
||||
S 1676 897412 1568177866 0 1568177866 0 "interfaces//../VX_define.v"
|
||||
S 227 897429 1568177888 0 1568177888 0 "interfaces//VX_branch_response_inter.v"
|
||||
S 212 897430 1568177888 0 1568177888 0 "interfaces//VX_csr_write_request_inter.v"
|
||||
S 373 897431 1568177888 0 1568177888 0 "interfaces//VX_dcache_request_inter.v"
|
||||
S 186 897432 1568177888 0 1568177888 0 "interfaces//VX_dcache_response_inter.v"
|
||||
S 282 897434 1568177888 0 1568177888 0 "interfaces//VX_forward_exe_inter.v"
|
||||
S 327 897435 1568177888 0 1568177888 0 "interfaces//VX_forward_mem_inter.v"
|
||||
S 204 897436 1568177888 0 1568177888 0 "interfaces//VX_forward_reqeust_inter.v"
|
||||
S 273 897437 1568177888 0 1568177888 0 "interfaces//VX_forward_response_inter.v"
|
||||
S 313 897438 1568177888 0 1568177888 0 "interfaces//VX_forward_wb_inter.v"
|
||||
S 833 897439 1568177888 0 1568177888 0 "interfaces//VX_frE_to_bckE_req_inter.v"
|
||||
S 253 897441 1568177888 0 1568177888 0 "interfaces//VX_gpr_clone_inter.v"
|
||||
S 173 897442 1568177888 0 1568177888 0 "interfaces//VX_gpr_jal_inter.v"
|
||||
S 193 897443 1568177888 0 1568177888 0 "interfaces//VX_gpr_read_inter.v"
|
||||
S 293 897444 1568177888 0 1568177888 0 "interfaces//VX_gpr_wspawn_inter.v"
|
||||
S 159 897445 1568177890 0 1568177890 0 "interfaces//VX_icache_request_inter.v"
|
||||
S 194 897446 1568177890 0 1568177890 0 "interfaces//VX_icache_response_inter.v"
|
||||
S 366 897447 1568177890 0 1568177890 0 "interfaces//VX_inst_mem_wb_inter.v"
|
||||
S 237 897448 1568177890 0 1568177890 0 "interfaces//VX_inst_meta_inter.v"
|
||||
S 205 897449 1568177890 0 1568177890 0 "interfaces//VX_jal_response_inter.v"
|
||||
S 557 897450 1568177890 0 1568177890 0 "interfaces//VX_mem_req_inter.v"
|
||||
S 348 897451 1568177890 0 1568177890 0 "interfaces//VX_mw_wb_inter.v"
|
||||
S 297 897452 1568177890 0 1568177890 0 "interfaces//VX_warp_ctl_inter.v"
|
||||
S 273 897453 1568177890 0 1568177890 0 "interfaces//VX_wb_inter.v"
|
||||
T 1312387 897481 1568178034 0 1568178034 0 "obj_dir/VVortex.cpp"
|
||||
T 23516 897479 1568178032 0 1568178032 0 "obj_dir/VVortex.h"
|
||||
T 1791 897581 1568178034 0 1568178034 0 "obj_dir/VVortex.mk"
|
||||
T 914 897569 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_branch_response_inter.cpp"
|
||||
T 1029 897568 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_branch_response_inter.h"
|
||||
T 1210 897565 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_dcache_request_inter.cpp"
|
||||
T 1135 897564 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_dcache_request_inter.h"
|
||||
T 988 897563 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_dcache_response_inter.cpp"
|
||||
T 1045 897562 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_dcache_response_inter.h"
|
||||
T 1059 897567 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp"
|
||||
T 1142 897566 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.h"
|
||||
T 884 897577 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.cpp"
|
||||
T 1008 897576 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.h"
|
||||
T 865 897573 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_inst_meta_inter.cpp"
|
||||
T 987 897572 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_inst_meta_inter.h"
|
||||
T 885 897575 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_mem_req_inter.cpp"
|
||||
T 1005 897574 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_mem_req_inter.h"
|
||||
T 902 897571 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_warp_ctl_inter.cpp"
|
||||
T 1017 897570 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_warp_ctl_inter.h"
|
||||
T 825 897579 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_wb_inter.cpp"
|
||||
T 954 897578 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_wb_inter.h"
|
||||
T 3499 897478 1568178032 0 1568178032 0 "obj_dir/VVortex__Syms.cpp"
|
||||
T 1855 897477 1568178032 0 1568178032 0 "obj_dir/VVortex__Syms.h"
|
||||
T 2113 897582 1568178034 0 1568178034 0 "obj_dir/VVortex__ver.d"
|
||||
T 0 0 1568178034 0 1568178034 0 "obj_dir/VVortex__verFiles.dat"
|
||||
T 1530 897580 1568178034 0 1568178034 0 "obj_dir/VVortex_classes.mk"
|
||||
S 1884 897454 1568177900 0 1568177900 0 "pipe_regs//VX_d_e_reg.v"
|
||||
S 1538 897455 1568177900 0 1568177900 0 "pipe_regs//VX_e_m_reg.v"
|
||||
S 751 897456 1568177900 0 1568177900 0 "pipe_regs//VX_f_d_reg.v"
|
||||
S 688 897457 1568177900 0 1568177900 0 "pipe_regs//VX_m_w_reg.v"
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
30
rtl/quartus/VX_gpr_syn.qpf
Normal file
30
rtl/quartus/VX_gpr_syn.qpf
Normal file
@@ -0,0 +1,30 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 18.0.0 Build 219 04/25/2018 SJ Pro Edition
|
||||
# Date created = 00:18:19 September 11, 2019
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "18.0"
|
||||
DATE = "00:18:19 September 11, 2019"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "VX_gpr_syn"
|
||||
63
rtl/quartus/VX_gpr_syn.qsf
Normal file
63
rtl/quartus/VX_gpr_syn.qsf
Normal file
@@ -0,0 +1,63 @@
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:18:19 SEPTEMBER 11, 2019"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Pro Edition"
|
||||
set_global_assignment -name FAMILY "Arria 10"
|
||||
set_global_assignment -name DEVICE 10AX115N4F45I3SG
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY VX_gpr_syn
|
||||
set_global_assignment -name SEARCH_PATH ../
|
||||
set_global_assignment -name VERILOG_FILE ../VX_define.v
|
||||
set_global_assignment -name VERILOG_FILE ../byte_enabled_simple_dual_port_ram.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_branch_response_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_csr_write_request_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_request_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_response_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_csr_response_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_exe_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_mem_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_reqeust_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_response_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_wb_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_frE_to_bckE_req_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_clone_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_jal_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_read_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_wspawn_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_icache_request_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_icache_response_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_mem_wb_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_meta_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_jal_response_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_mem_req_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_mw_wb_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_warp_ctl_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_wb_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_d_e_reg.v
|
||||
set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_e_m_reg.v
|
||||
set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_f_d_reg.v
|
||||
set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_m_w_reg.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_alu.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_back_end.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_context.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_context_slave.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_csr_handler.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_decode.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_execute.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_fetch.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_forwarding.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_front_end.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_generic_register.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_gpr.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_gpr_wrapper.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_gpr_syn.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_memory.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_register_file.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_register_file_master_slave.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_register_file_slave.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_warp.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_writeback.v
|
||||
set_global_assignment -name VERILOG_FILE ../Vortex.v
|
||||
set_global_assignment -name SDC_FILE vortex.sdc
|
||||
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin
|
||||
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
|
||||
1
rtl/quartus/asm.chg
Normal file
1
rtl/quartus/asm.chg
Normal file
@@ -0,0 +1 @@
|
||||
done
|
||||
1
rtl/quartus/fit.chg
Normal file
1
rtl/quartus/fit.chg
Normal file
@@ -0,0 +1 @@
|
||||
done
|
||||
1
rtl/quartus/map.chg
Normal file
1
rtl/quartus/map.chg
Normal file
@@ -0,0 +1 @@
|
||||
Wed Sep 11 00:18:22 2019
|
||||
@@ -21,6 +21,8 @@ set_global_assignment -name SEARCH_PATH ../
|
||||
|
||||
set_global_assignment -name VERILOG_FILE ../VX_define.v
|
||||
|
||||
set_global_assignment -name VERILOG_FILE ../byte_enabled_simple_dual_port_ram.v
|
||||
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_branch_response_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_csr_write_request_inter.v
|
||||
set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_request_inter.v
|
||||
|
||||
27
rtl/quartus/smart.log
Normal file
27
rtl/quartus/smart.log
Normal file
@@ -0,0 +1,27 @@
|
||||
Info (292036): Thank you for using the Quartus Prime software 30-day evaluation. You have 0 days remaining (until Sep 11, 2019) to use the Quartus Prime software with compilation and simulation support.
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Shell
|
||||
Info: Version 18.0.0 Build 219 04/25/2018 SJ Pro Edition
|
||||
Info: Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Info: Your use of Intel Corporation's design tools, logic functions
|
||||
Info: and other software and tools, and its AMPP partner logic
|
||||
Info: functions, and any output files from any of the foregoing
|
||||
Info: (including device programming or simulation files), and any
|
||||
Info: associated documentation or information are expressly subject
|
||||
Info: to the terms and conditions of the Intel Program License
|
||||
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
Info: the Intel FPGA IP License Agreement, or other applicable license
|
||||
Info: agreement, including, without limitation, that your use is for
|
||||
Info: the sole purpose of programming logic devices manufactured by
|
||||
Info: Intel and sold by Intel or its authorized distributors. Please
|
||||
Info: refer to the applicable agreement for further details.
|
||||
Info: Processing started: Wed Sep 11 00:18:22 2019
|
||||
Info: Command: quartus_sh --determine_smart_action VX_gpr_syn
|
||||
Info: Quartus(args): VX_gpr_syn
|
||||
Info: SMART_ACTION = SOURCE
|
||||
Info (23030): Evaluation of Tcl script /tools/reconfig/intel/18.0/quartus/common/tcl/internal/qsh_smart.tcl was successful
|
||||
Info: Quartus Prime Shell was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 687 megabytes
|
||||
Info: Processing ended: Wed Sep 11 00:18:22 2019
|
||||
Info: Elapsed time: 00:00:00
|
||||
Info: Total CPU time (on all processors): 00:00:00
|
||||
1
rtl/quartus/sta.chg
Normal file
1
rtl/quartus/sta.chg
Normal file
@@ -0,0 +1 @@
|
||||
done
|
||||
1
rtl/quartus/syn.chg
Normal file
1
rtl/quartus/syn.chg
Normal file
@@ -0,0 +1 @@
|
||||
done
|
||||
@@ -3,5 +3,5 @@
|
||||
# of forwarding stalls: 0
|
||||
# of branch stalls: 0
|
||||
# CPI: 1.00015
|
||||
# time to simulate: 2.22726e-314 milliseconds
|
||||
# time to simulate: 2.18298e-314 milliseconds
|
||||
# GRADE: Failed on test: 4294967295
|
||||
|
||||
@@ -1,5 +1,3 @@
|
||||
|
||||
|
||||
#include "test_bench.h"
|
||||
|
||||
#define NUM_TESTS 46
|
||||
@@ -88,6 +86,3 @@ int main(int argc, char **argv)
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -1,5 +1,3 @@
|
||||
|
||||
|
||||
// C++ libraries
|
||||
#include <utility>
|
||||
#include <iostream>
|
||||
@@ -397,14 +395,4 @@ bool Vortex::simulate(std::string file_to_simulate)
|
||||
|
||||
|
||||
return (status == 1);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
}
|
||||
215904
rtl/worst_case_paths.rpt
215904
rtl/worst_case_paths.rpt
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user