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kernels/hw/rtl
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Blaise Tine 625689796f minor update
2021-04-04 23:42:57 -07:00
..
afu
fixed FCVT timing critical path
2021-03-18 13:26:36 -07:00
cache
minor update
2021-04-04 23:42:57 -07:00
fp_cores
fpu dpi update
2021-03-31 02:36:34 -07:00
interfaces
csr minor update
2021-03-08 03:46:07 -08:00
libs
adding empty to index_buffer
2021-03-30 10:15:42 -07:00
tex_unit
modelsim fixes && pipeline optimization
2020-07-28 14:20:23 -07:00
.DS_Store
project directories reorganization
2020-04-14 06:35:20 -04:00
.gitignore
fix opae build
2020-04-20 12:51:42 -07:00
Vortex.v
minor update
2021-03-21 11:40:54 -07:00
VX_alu_unit.v
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
2021-03-04 20:51:03 -08:00
VX_cluster.v
minor update
2021-03-21 11:40:54 -07:00
VX_commit.v
moving MUL unit into ALU unit
2021-02-23 13:49:02 -08:00
VX_config.vh
using shiftreg-based skid buffers
2021-02-28 02:20:09 -08:00
VX_core.v
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
2021-03-04 20:51:03 -08:00
VX_csr_arb.v
minor update
2021-02-12 08:52:06 -08:00
VX_csr_data.v
floating-point CSR fix
2021-03-01 01:46:41 -08:00
VX_csr_io_arb.v
csr minor update
2021-03-08 03:46:07 -08:00
VX_csr_unit.v
csr minor update
2021-03-08 03:46:07 -08:00
VX_databus_arb.v
databus optimization
2021-03-29 23:48:04 -07:00
VX_decode.v
minor updates
2021-04-04 04:04:41 -07:00
VX_define.vh
minor update
2021-02-27 21:54:55 -08:00
VX_execute.v
moving MUL unit into ALU unit
2021-02-23 13:49:02 -08:00
VX_fetch.v
cache request interfaces update
2021-02-10 20:55:04 -08:00
VX_fpu_unit.v
adding empty to index_buffer
2021-03-30 10:15:42 -07:00
VX_gpr_ram_f.v
minor update
2021-01-01 20:24:18 -08:00
VX_gpr_ram_i.v
fixed register file initialization to zero synthesis inference
2020-12-10 00:27:56 -08:00
VX_gpr_stage.v
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
2021-03-04 20:51:03 -08:00
VX_gpu_unit.v
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
2021-03-04 20:51:03 -08:00
VX_ibuffer.v
minor update - mux reordering to reduce critical path on input data
2021-03-21 11:43:57 -07:00
VX_icache_stage.v
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
2021-03-04 20:51:03 -08:00
VX_instr_demux.v
minor update
2021-03-22 23:04:35 -07:00
VX_ipdom_stack.v
critical path optimization - fpga fmax @4c = ~212 mhz
2020-12-26 03:28:32 -08:00
VX_issue.v
arrays logging
2021-04-02 02:20:15 -07:00
VX_lsu_unit.v
minor update
2021-04-04 17:57:35 -07:00
VX_mem_arb.v
performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
2020-12-19 02:45:06 -08:00
VX_mem_unit.v
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
2021-03-04 20:51:03 -08:00
VX_muldiv.v
moving MUL unit into ALU unit
2021-02-23 13:49:02 -08:00
VX_pipeline.v
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
2021-03-04 20:51:03 -08:00
VX_platform.vh
arrays logging
2021-04-02 02:20:15 -07:00
VX_print_instr.vh
minor update
2021-02-27 21:54:55 -08:00
VX_scope.vh
moving MUL unit into ALU unit
2021-02-23 13:49:02 -08:00
VX_scoreboard.v
lkg build rollout with 16cores optimization on arria10
2021-01-24 16:49:22 -08:00
VX_types.vh
FPU float<->int conversion optimization
2020-12-29 15:37:45 -08:00
VX_warp_sched.v
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
2021-03-04 20:51:03 -08:00
VX_writeback.v
relaxing commit back-pressure in writeback stage
2021-03-15 14:39:55 -07:00