77 lines
1.8 KiB
Verilog
77 lines
1.8 KiB
Verilog
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`include "VX_define.v"
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module VX_fetch (
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input wire clk,
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input wire reset,
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input wire in_branch_dir,
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input wire in_freeze,
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input wire[31:0] in_branch_dest,
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input wire in_branch_stall,
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input wire in_fwd_stall,
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input wire in_branch_stall_exe,
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input wire in_clone_stall,
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input wire in_jal,
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input wire[31:0] in_jal_dest,
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input wire in_interrupt,
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input wire in_debug,
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input wire[31:0] in_instruction,
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input wire in_thread_mask[`NT_M1:0],
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input wire in_change_mask,
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output wire[31:0] out_instruction,
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output wire out_delay,
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// output wire[1:0] out_warp_num,
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output wire[31:0] out_curr_PC,
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output wire out_valid[`NT_M1:0]
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);
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reg stall;
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reg[31:0] out_PC;
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// reg[1:0] warp_num;
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// initial begin
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// warp_num = 0;
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// end
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assign stall = in_clone_stall || in_branch_stall || in_fwd_stall || in_branch_stall_exe || in_interrupt || in_freeze || in_debug;
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wire[31:0] warp_pc;
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wire warp_valid[`NT_M1:0];
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VX_warp VX_Warp(
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.clk (clk),
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.reset (reset),
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.stall (stall),
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.in_thread_mask(in_thread_mask),
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.in_change_mask(in_change_mask),
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.in_jal (in_jal),
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.in_jal_dest (in_jal_dest),
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.in_branch_dir (in_branch_dir),
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.in_branch_dest(in_branch_dest),
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.out_PC (warp_pc),
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.out_valid (warp_valid)
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);
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assign out_PC = warp_pc;
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// always @(*) begin
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// $display("FETCH PC: %h (%h, %h, %h)",delete, delete, in_jal_dest, in_branch_dest);
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// end
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assign out_curr_PC = out_PC;
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assign out_valid = warp_valid;
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// assign out_warp_num = warp_num;
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assign out_delay = 0;
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assign out_instruction = stall ? 32'b0 : in_instruction;
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endmodule |