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Changed hierarchy + Identified private + public modules

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This commit is contained in:
felsabbagh3
2019-05-07 23:45:05 -07:00
parent 191ed73415
commit 79356c7ab1
20 changed files with 2602 additions and 694 deletions
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12
kernel/Makefile
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@@ -1,13 +1,13 @@
# COMP = /opt/riscv/bin/riscv32-unknown-elf-gcc
COMP = /opt/riscv/bin/riscv32-unknown-linux-gnu-gcc
COMP = /opt/riscv/bin/riscv32-unknown-elf-gcc
# COMP = /opt/riscv/bin/riscv32-unknown-linux-gnu-gcc
CC_FLAGS = -march=rv32im -mabi=ilp32 -O0 -Wl,-Bstatic,-T,linker.ld -ffreestanding -nostdlib
# DMP = /opt/riscv/bin/riscv32-unknown-elf-objdump
# CPY = /opt/riscv/bin/riscv32-unknown-elf-objcopy
DMP = /opt/riscv/bin/riscv32-unknown-elf-objdump
CPY = /opt/riscv/bin/riscv32-unknown-elf-objcopy
DMP = /opt/riscv/bin/riscv32-unknown-linux-gnu-objdump
CPY = /opt/riscv/bin/riscv32-unknown-linux-gnu-objcopy
# DMP = /opt/riscv/bin/riscv32-unknown-linux-gnu-objdump
# CPY = /opt/riscv/bin/riscv32-unknown-linux-gnu-objcopy
VX_LIB = ./vx_os/vx_back/vx_back.s ./vx_os/vx_back/vx_back.c ./vx_os/vx_util/queue.s
VX_IO = ./vx_os/vx_io/vx_io.s ./vx_os/vx_io/vx_io.c

2
kernel/vortex_test.dump
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@@ -7,7 +7,7 @@ Disassembly of section .text:
80000000 <_start>:
80000000: 00100513 li a0,1
80000004: 02051073 csrw 0x20,a0
80000008: 00100513 li a0,1
80000008: 00200513 li a0,2
8000000c: 02151073 csrw 0x21,a0
80000010: f1401073 csrw mhartid,zero
80000014: 30101073 csrw misa,zero

BIN
kernel/vortex_test.elf
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Binary file not shown.

2
kernel/vortex_test.hex
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@@ -1,5 +1,5 @@
:0200000480007A
:10000000130510007310050213051000731015027C
:10000000130510007310050213052000731015026C
:10001000731040F17310103037F1FF7FEF0080193B
:10002000EF10C06D73000000938B0600130D0700E6
:10003000130F01009303050013051000635C7500A6

2
kernel/vx_os/vx_back/vx_back.s
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@@ -8,7 +8,7 @@
_start:
li a0, 1 # Num Warps
csrw 0x20, a0 # Setting the number of available warps
li a0, 1 # Num Threads
li a0, 2 # Num Threads
csrw 0x21, a0 # Setting the number of available threads
csrw mhartid,zero
csrw misa,zero

93
rtl/VX_context.v Normal file
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@@ -0,0 +1,93 @@
`include "VX_define.v"
module VX_context (
input wire clk,
input wire in_valid[`NT_M1:0],
input wire in_write_register,
input wire[4:0] in_rd,
input wire[31:0] in_write_data[`NT_M1:0],
input wire[4:0] in_src1,
input wire[4:0] in_src2,
input wire[31:0] in_curr_PC,
input wire in_is_clone,
input wire in_is_jal,
input wire in_src1_fwd,
input wire[31:0] in_src1_fwd_data[`NT_M1:0],
input wire in_src2_fwd,
input wire[31:0] in_src2_fwd_data[`NT_M1:0],
output reg[31:0] out_a_reg_data[`NT_M1:0],
output reg[31:0] out_b_reg_data[`NT_M1:0],
output wire out_clone_stall
);
wire[31:0] rd1_register[`NT_M1:0];
wire[31:0] rd2_register[`NT_M1:0];
/* verilator lint_off UNUSED */
wire[31:0] clone_regsiters[31:0];
/* verilator lint_on UNUSED */
VX_register_file vx_register_file_master(
.clk (clk),
.in_valid (in_valid[0]),
.in_write_register (in_write_register),
.in_rd (in_rd),
.in_data (in_write_data[0]),
.in_src1 (in_src1),
.in_src2 (in_src2),
.out_regs (clone_regsiters),
.out_src1_data (rd1_register[0]),
.out_src2_data (rd2_register[0])
);
genvar index;
generate
for (index=1; index < `NT; index=index+1)
begin: gen_code_label
wire to_clone;
assign to_clone = (index == rd1_register[0]) && (state_stall == 1);
VX_register_file_slave vx_register_file_slave(
.clk (clk),
.in_valid (in_valid[index]),
.in_write_register (in_write_register),
.in_rd (in_rd),
.in_data (in_write_data[index]),
.in_src1 (in_src1),
.in_src2 (in_src2),
.in_clone (in_is_clone),
.in_to_clone (to_clone),
.in_regs (clone_regsiters),
.out_src1_data (rd1_register[index]),
.out_src2_data (rd2_register[index])
);
end
endgenerate
reg[5:0] state_stall = 0;
always @(posedge clk) begin
if ((in_is_clone) && state_stall == 0) begin
state_stall <= 10;
// $display("CLONEEE BITCH %d, 1 =? %h = %h -- %d", state_stall, rd1_register[0], to_clone_1, in_is_clone);
end else if (state_stall == 1) begin
// $display("ENDING CLONE, 1 =? %h = %h -- %d", rd1_register[0], to_clone_1, in_is_clone);
state_stall <= 0;
end else if (state_stall > 0) begin
state_stall <= state_stall - 1;
// $display("CLONEEE BITCH %d, 1 =? %h = %h -- %d", state_stall, rd1_register[0], to_clone_1, in_is_clone);
end
end
genvar index_out_reg;
generate
for (index_out_reg = 0; index_out_reg < `NT; index_out_reg = index_out_reg + 1)
begin
assign out_a_reg_data[index_out_reg] = ( (in_is_jal == 1'b1) ? in_curr_PC : ((in_src1_fwd == 1'b1) ? in_src1_fwd_data[index_out_reg] : rd1_register[index_out_reg]));
assign out_b_reg_data[index_out_reg] = (in_src2_fwd == 1'b1) ? in_src2_fwd_data[index_out_reg] : rd2_register[index_out_reg];
end
endgenerate
assign out_clone_stall = ((state_stall == 0) && in_is_clone) || ((state_stall != 1) && in_is_clone);
endmodule

138
rtl/VX_decode.v
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@@ -49,10 +49,6 @@ module VX_decode(
wire[6:0] curr_opcode;
wire[31:0] rd1_register[`NT_M1:0];
wire[31:0] rd2_register[`NT_M1:0];
wire is_itype;
wire is_rtype;
wire is_stype;
@@ -107,104 +103,31 @@ module VX_decode(
reg[4:0] alu_op;
reg[4:0] mul_alu;
// wire[31:0] internal_rd1;
// wire[31:0] internal_rd2;
VX_context VX_Context(
.clk (clk),
.in_valid (in_wb_valid),
.in_rd (in_rd),
.in_src1 (out_rs1),
.in_src2 (out_rs2),
.in_curr_PC (in_curr_PC),
.in_is_clone (is_clone),
.in_is_jal (is_jal),
.in_src1_fwd (in_src1_fwd),
.in_src1_fwd_data (in_src1_fwd_data),
.in_src2_fwd (in_src2_fwd),
.in_src2_fwd_data (in_src2_fwd_data),
.in_write_register(write_register),
.in_write_data (in_write_data),
.out_a_reg_data (out_a_reg_data),
.out_b_reg_data (out_b_reg_data),
.out_clone_stall (out_clone_stall)
);
// VX_register_file vx_register_file_0(
// .clk(clk),
// .in_valid(in_wb_valid[0]),
// .in_write_register(write_register),
// .in_rd(in_rd),
// .in_data(in_write_data[1:0]),
// .in_src1(out_rs1),
// .in_src2(out_rs2),
// .out_src1_data(rd1_register),
// .out_src2_data(rd2_register)
// );
// VX_register_file vx_register_file_1(
// .clk(clk),
// .in_valid(in_wb_valid),
// .in_write_register(write_register),
// .in_rd(in_rd),
// .in_data(in_write_data),
// .in_src1(out_rs1),
// .in_src2(out_rs2),
// .out_src1_data(rd1_register),
// .out_src2_data(rd2_register)
// );
assign out_valid = in_valid;
assign write_register = (in_wb != 2'h0) ? (1'b1) : (1'b0);
// always @(*) begin
// $display("DECODE PC: %h",in_curr_PC);
// end
// always @(posedge clk) begin
// $display("Decode: curr_pc: %h", in_curr_PC);
// end
/* verilator lint_off UNUSED */
wire[31:0] clone_regsiters[31:0];
/* verilator lint_on UNUSED */
VX_register_file vx_register_file_master(
.clk (clk),
.in_valid (in_wb_valid[0]),
.in_write_register (write_register),
.in_rd (in_rd),
.in_data (in_write_data[0]),
.in_src1 (out_rs1),
.in_src2 (out_rs2),
.out_regs (clone_regsiters),
.out_src1_data (rd1_register[0]),
.out_src2_data (rd2_register[0])
);
// wire to_clone_1 = (1 == rd1_register[0]) && (state_stall == 1);
// VX_register_file_slave vx_register_file_slave(
// .clk (clk),
// .in_valid (in_wb_valid[1]),
// .in_write_register (write_register),
// .in_rd (in_rd),
// .in_data (in_write_data[1]),
// .in_src1 (out_rs1),
// .in_src2 (out_rs2),
// .in_clone (is_clone),
// .in_to_clone (to_clone_1),
// .in_regs (clone_regsiters),
// .out_src1_data (rd1_register[1]),
// .out_src2_data (rd2_register[1])
// );
genvar index;
generate
for (index=1; index < `NT; index=index+1)
begin: gen_code_label
wire to_clone;
assign to_clone = (index == rd1_register[0]) && (state_stall == 1);
VX_register_file_slave vx_register_file_slave(
.clk (clk),
.in_valid (in_wb_valid[index]),
.in_write_register (write_register),
.in_rd (in_rd),
.in_data (in_write_data[index]),
.in_src1 (out_rs1),
.in_src2 (out_rs2),
.in_clone (is_clone),
.in_to_clone (to_clone),
.in_regs (clone_regsiters),
.out_src1_data (rd1_register[index]),
.out_src2_data (rd2_register[index])
);
end
endgenerate
assign curr_opcode = in_instruction[6:0];
@@ -278,32 +201,11 @@ module VX_decode(
// $display("Decode inst: %h", in_instruction);
// end
reg[5:0] state_stall = 0;
always @(posedge clk) begin
if ((is_clone) && state_stall == 0) begin
state_stall <= 10;
// $display("CLONEEE BITCH %d, 1 =? %h = %h -- %d", state_stall, rd1_register[0], to_clone_1, is_clone);
end else if (state_stall == 1) begin
// $display("ENDING CLONE, 1 =? %h = %h -- %d", rd1_register[0], to_clone_1, is_clone);
state_stall <= 0;
end else if (state_stall > 0) begin
state_stall <= state_stall - 1;
// $display("CLONEEE BITCH %d, 1 =? %h = %h -- %d", state_stall, rd1_register[0], to_clone_1, is_clone);
end
end
assign out_clone_stall = ((state_stall == 0) && is_clone) || ((state_stall != 1) && is_clone);
// ch_print("DECODE: PC: {0}, INSTRUCTION: {1}", in_curr_PC, in_instruction);
genvar index_out_reg;
generate
for (index_out_reg = 0; index_out_reg < `NT; index_out_reg = index_out_reg + 1)
begin
assign out_a_reg_data[index_out_reg] = ( (is_jal == 1'b1) ? in_curr_PC : ((in_src1_fwd == 1'b1) ? in_src1_fwd_data[index_out_reg] : rd1_register[index_out_reg]));
assign out_b_reg_data[index_out_reg] = (in_src2_fwd == 1'b1) ? in_src2_fwd_data[index_out_reg] : rd2_register[index_out_reg];
end
endgenerate
// assign out_reg_data[0] = ( (is_jal == 1'b1) ? in_curr_PC : ((in_src1_fwd == 1'b1) ? in_src1_fwd_data[0] : rd1_register[0]));
// assign out_reg_data[1] = (in_src2_fwd == 1'b1) ? in_src2_fwd_data[0] : rd2_register[0];

4
rtl/VX_define.h
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@@ -1,7 +1,7 @@
#define NT 1
#define NT_M1 0
#define NT 2
#define NT_M1 1
#define R_INST 51
#define L_INST 3

4
rtl/VX_define.v
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@@ -1,6 +1,6 @@
`define NT 1
`define NT_M1 0
`define NT 2
`define NT_M1 1
`define R_INST 7'd51

96
rtl/VX_fetch.v
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@@ -2,80 +2,60 @@
`include "VX_define.v"
module VX_fetch (
input wire clk,
input wire reset,
input wire in_branch_dir,
input wire in_freeze,
input wire[31:0] in_branch_dest,
input wire in_branch_stall,
input wire in_fwd_stall,
input wire in_branch_stall_exe,
input wire in_clone_stall,
input wire in_jal,
input wire[31:0] in_jal_dest,
input wire in_interrupt,
input wire in_debug,
input wire[31:0] in_instruction,
input wire in_thread_mask[`NT_M1:0],
input wire in_change_mask,
input wire clk,
input wire reset,
input wire in_branch_dir,
input wire in_freeze,
input wire[31:0] in_branch_dest,
input wire in_branch_stall,
input wire in_fwd_stall,
input wire in_branch_stall_exe,
input wire in_clone_stall,
input wire in_jal,
input wire[31:0] in_jal_dest,
input wire in_interrupt,
input wire in_debug,
input wire[31:0] in_instruction,
input wire in_thread_mask[`NT_M1:0],
input wire in_change_mask,
output wire[31:0] out_instruction,
output wire out_delay,
output wire[31:0] out_curr_PC,
output wire out_valid[`NT_M1:0]
output wire[31:0] out_instruction,
output wire out_delay,
// output wire[1:0] out_warp_num,
output wire[31:0] out_curr_PC,
output wire out_valid[`NT_M1:0]
);
reg stall;
reg[31:0] out_PC;
// reg[1:0] warp_num;
reg valid[`NT_M1:0];
integer ini_cur_th = 0;
genvar out_cur_th;
initial begin
for (ini_cur_th = 1; ini_cur_th < `NT; ini_cur_th=ini_cur_th+1)
valid[ini_cur_th] = 0; // Thread 1 active
valid[0] = 1;
end
always @(*) begin : proc_
if (in_change_mask) begin
// $display("CHANGING MASK: [%d %d]",in_thread_mask[0], in_thread_mask[1]);
assign valid = in_thread_mask;
end
end
// initial begin
// warp_num = 0;
// end
assign out_delay = 0;
assign stall = in_clone_stall || in_branch_stall || in_fwd_stall || in_branch_stall_exe || in_interrupt || in_freeze || in_debug;
assign out_instruction = stall ? 32'b0 : in_instruction;
// assign out_instruction = in_instruction;
generate
for (out_cur_th = 0; out_cur_th < `NT; out_cur_th = out_cur_th+1)
assign out_valid[out_cur_th] = in_change_mask ? in_thread_mask[out_cur_th] : stall ? 1'b0 : valid[out_cur_th];
endgenerate
wire[31:0] warp_pc;
wire warp_valid[`NT_M1:0];
VX_warp VX_Warp(
.clk (clk),
.reset (reset),
.stall (stall),
.in_thread_mask(in_thread_mask),
.in_change_mask(in_change_mask),
.in_jal (in_jal),
.in_jal_dest (in_jal_dest),
.in_branch_dir (in_branch_dir),
.in_branch_dest(in_branch_dest),
.out_PC (warp_pc)
.out_PC (warp_pc),
.out_valid (warp_valid)
);
@@ -86,15 +66,11 @@ module VX_fetch (
// end
assign out_curr_PC = out_PC;
// always @(*) begin
// $display("Fetch out pc: %h", out_PC);
// end
assign out_curr_PC = out_PC;
assign out_valid = warp_valid;
// assign out_warp_num = warp_num;
assign out_delay = 0;
assign out_instruction = stall ? 32'b0 : in_instruction;

52
rtl/VX_warp.v
View File

@@ -1,24 +1,51 @@
`include "VX_define.v"
module VX_warp (
input wire clk,
input wire reset,
input wire stall,
input wire in_jal,
input wire[31:0] in_jal_dest,
input wire in_branch_dir,
input wire[31:0] in_branch_dest,
input wire clk,
input wire reset,
input wire stall,
input wire in_thread_mask[`NT_M1:0],
input wire in_change_mask,
input wire in_jal,
input wire[31:0] in_jal_dest,
input wire in_branch_dir,
input wire[31:0] in_branch_dest,
output wire[31:0] out_PC
output wire[31:0] out_PC,
output wire out_valid[`NT_M1:0]
);
reg[31:0] real_PC;
var[31:0] temp_PC;
var[31:0] use_PC;
reg valid[`NT_M1:0];
integer ini_cur_th = 0;
initial begin
real_PC = 0;
for (ini_cur_th = 1; ini_cur_th < `NT; ini_cur_th=ini_cur_th+1)
valid[ini_cur_th] = 0; // Thread 1 active
valid[0] = 1;
end
var[31:0] temp_PC;
always @(*) begin
if (in_change_mask) begin
assign valid = in_thread_mask;
end
end
genvar out_cur_th;
generate
for (out_cur_th = 0; out_cur_th < `NT; out_cur_th = out_cur_th+1)
assign out_valid[out_cur_th] = in_change_mask ? in_thread_mask[out_cur_th] : stall ? 1'b0 : valid[out_cur_th];
endgenerate
always @(*) begin
if (in_jal == 1'b1) begin
temp_PC = in_jal_dest;
@@ -29,13 +56,16 @@ module VX_warp (
end
end
assign use_PC = temp_PC;
assign out_PC = temp_PC;
always @(posedge clk or posedge reset) begin
if (reset) begin
real_PC <= 0;
end else if (stall != 1'b1) begin
real_PC <= temp_PC + 32'h4;
end else if (stall == 1'b0) begin
real_PC <= use_PC + 32'h4;
end else begin
real_PC <= use_PC;
end
end

BIN
rtl/obj_dir/VVortex
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2597
rtl/obj_dir/VVortex.cpp
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File diff suppressed because it is too large Load Diff

261
rtl/obj_dir/VVortex.h
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@@ -27,10 +27,10 @@ VL_MODULE(VVortex) {
VL_OUT8(out_cache_driver_in_mem_write,2,0);
VL_IN(fe_instruction,31,0);
VL_OUT(curr_PC,31,0);
VL_IN(in_cache_driver_out_data[1],31,0);
VL_OUT(out_cache_driver_in_address[1],31,0);
VL_OUT8(out_cache_driver_in_valid[1],0,0);
VL_OUT(out_cache_driver_in_data[1],31,0);
VL_IN(in_cache_driver_out_data[2],31,0);
VL_OUT(out_cache_driver_in_address[2],31,0);
VL_OUT8(out_cache_driver_in_valid[2],0,0);
VL_OUT(out_cache_driver_in_data[2],31,0);
// LOCAL SIGNALS
// Internals; generally not touched by application code
@@ -44,6 +44,8 @@ VL_MODULE(VVortex) {
VL_SIG8(Vortex__DOT__decode_change_mask,0,0);
VL_SIG8(Vortex__DOT__execute_branch_stall,0,0);
VL_SIG8(Vortex__DOT__forwarding_fwd_stall,0,0);
VL_SIG8(Vortex__DOT__forwarding_src1_fwd,0,0);
VL_SIG8(Vortex__DOT__forwarding_src2_fwd,0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__stall,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_itype,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_csr,0,0);
@@ -51,8 +53,8 @@ VL_MODULE(VVortex) {
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_jalrs,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_jmprt,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__mul_alu,4,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__temp_final_alu,4,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__rd,4,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__alu_op,4,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__wb,1,0);
@@ -97,133 +99,156 @@ VL_MODULE(VVortex) {
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__curr_PC,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__jal_offset,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__PC_next,31,0);
};
struct {
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__csr_result,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__curr_PC,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__branch_offset,31,0);
};
struct {
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__jal_dest,31,0);
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__PC_next,31,0);
VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__cycle,63,0);
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__instret,63,0);
VL_SIG8(Vortex__DOT__fetch_valid[1],0,0);
VL_SIG8(Vortex__DOT__f_d_valid[1],0,0);
VL_SIG(Vortex__DOT__decode_a_reg_data[1],31,0);
VL_SIG(Vortex__DOT__decode_b_reg_data[1],31,0);
VL_SIG8(Vortex__DOT__decode_valid[1],0,0);
VL_SIG8(Vortex__DOT__decode_thread_mask[1],0,0);
VL_SIG(Vortex__DOT__d_e_a_reg_data[1],31,0);
VL_SIG(Vortex__DOT__d_e_b_reg_data[1],31,0);
VL_SIG8(Vortex__DOT__d_e_valid[1],0,0);
VL_SIG(Vortex__DOT__execute_alu_result[1],31,0);
VL_SIG(Vortex__DOT__execute_b_reg_data[1],31,0);
VL_SIG8(Vortex__DOT__execute_valid[1],0,0);
VL_SIG(Vortex__DOT__e_m_alu_result[1],31,0);
VL_SIG(Vortex__DOT__e_m_b_reg_data[1],31,0);
VL_SIG8(Vortex__DOT__e_m_valid[1],0,0);
VL_SIG(Vortex__DOT__memory_alu_result[1],31,0);
VL_SIG(Vortex__DOT__memory_mem_result[1],31,0);
VL_SIG8(Vortex__DOT__memory_valid[1],0,0);
VL_SIG(Vortex__DOT__m_w_alu_result[1],31,0);
VL_SIG(Vortex__DOT__m_w_mem_result[1],31,0);
VL_SIG8(Vortex__DOT__m_w_valid[1],0,0);
VL_SIG(Vortex__DOT__writeback_write_data[1],31,0);
VL_SIG(Vortex__DOT__forwarding_src1_fwd_data[1],31,0);
VL_SIG(Vortex__DOT__forwarding_src2_fwd_data[1],31,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__valid[1],0,0);
VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid[1],0,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__rd1_register[1],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__rd2_register[1],31,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__jalrs_thread_mask[1],0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__jmprt_thread_mask[1],0,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__vx_register_file_master__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[1],31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[1],31,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid[1],0,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[1],31,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid_z[1],0,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__alu_result[1],31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__a_reg_data[1],31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[1],31,0);
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__valid[1],0,0);
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__alu_result[1],31,0);
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__mem_result[1],31,0);
VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__valid[1],0,0);
VL_SIG(Vortex__DOT__vx_writeback__DOT__out_pc_data[1],31,0);
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[1],31,0);
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[1],31,0);
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[1],31,0);
VL_SIG8(Vortex__DOT__fetch_valid[2],0,0);
VL_SIG8(Vortex__DOT__f_d_valid[2],0,0);
VL_SIG(Vortex__DOT__decode_a_reg_data[2],31,0);
VL_SIG(Vortex__DOT__decode_b_reg_data[2],31,0);
VL_SIG8(Vortex__DOT__decode_valid[2],0,0);
VL_SIG8(Vortex__DOT__decode_thread_mask[2],0,0);
VL_SIG(Vortex__DOT__d_e_a_reg_data[2],31,0);
VL_SIG(Vortex__DOT__d_e_b_reg_data[2],31,0);
VL_SIG8(Vortex__DOT__d_e_valid[2],0,0);
VL_SIG(Vortex__DOT__execute_alu_result[2],31,0);
VL_SIG(Vortex__DOT__execute_b_reg_data[2],31,0);
VL_SIG8(Vortex__DOT__execute_valid[2],0,0);
VL_SIG(Vortex__DOT__e_m_alu_result[2],31,0);
VL_SIG(Vortex__DOT__e_m_b_reg_data[2],31,0);
VL_SIG8(Vortex__DOT__e_m_valid[2],0,0);
VL_SIG(Vortex__DOT__memory_alu_result[2],31,0);
VL_SIG(Vortex__DOT__memory_mem_result[2],31,0);
VL_SIG8(Vortex__DOT__memory_valid[2],0,0);
VL_SIG(Vortex__DOT__m_w_alu_result[2],31,0);
VL_SIG(Vortex__DOT__m_w_mem_result[2],31,0);
VL_SIG8(Vortex__DOT__m_w_valid[2],0,0);
VL_SIG(Vortex__DOT__writeback_write_data[2],31,0);
VL_SIG(Vortex__DOT__forwarding_src1_fwd_data[2],31,0);
VL_SIG(Vortex__DOT__forwarding_src2_fwd_data[2],31,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_valid[2],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__valid[2],0,0);
VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid[2],0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__jalrs_thread_mask[2],0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__jmprt_thread_mask[2],0,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd1_register[2],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd2_register[2],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[2],31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[2],31,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid[2],0,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[2],31,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid_z[2],0,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__alu_result[2],31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__a_reg_data[2],31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[2],31,0);
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__valid[2],0,0);
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__alu_result[2],31,0);
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__mem_result[2],31,0);
VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__valid[2],0,0);
VL_SIG(Vortex__DOT__vx_writeback__DOT__out_pc_data[2],31,0);
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[2],31,0);
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[2],31,0);
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[2],31,0);
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__csr[4096],11,0);
};
// LOCAL VARIABLES
// Internals; generally not touched by application code
// Begin mtask footprint all:
VL_SIG8(__Vtableidx1,2,0);
VL_SIG8(__Vclklast__TOP__clk,0,0);
VL_SIG8(__Vclklast__TOP__reset,0,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_master__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_master__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_fetch__out_valid[1],0,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask[1],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[1],0,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[1],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_thread_mask[1],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_valid[1],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[1],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[1],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[1],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[1],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[1],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_write_data[1],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_valid[1],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[1],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[1],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[1],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[1],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[1],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[1],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_execute__out_valid[1],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[1],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_alu_result[1],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_execute__in_valid[1],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[1],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[1],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[1],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[1],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[1],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[1],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[1],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[1],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[1],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[1],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[1],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_valid[1],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_mem_result[1],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_alu_result[1],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[1],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_memory__in_valid[1],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_rd2[1],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_alu_result[1],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[1],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[1],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[1],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[1],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[1],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[1],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_writeback__out_write_data[1],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[1],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[1],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[1],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[1],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[1],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[1],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[1],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[1],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[1],31,0);
// Anonymous structures to workaround compiler member-count bugs
struct {
// Begin mtask footprint all:
VL_SIG8(__Vtableidx1,2,0);
VL_SIG8(__Vclklast__TOP__clk,0,0);
VL_SIG8(__Vclklast__TOP__reset,0,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_fetch__out_valid[2],0,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask[2],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[2],0,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[2],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_thread_mask[2],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_write_data[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_valid[2],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[2],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_execute__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_alu_result[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_execute__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[2],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[2],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[2],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_mem_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_alu_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_memory__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_rd2[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_alu_result[2],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_writeback__out_write_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[2],31,0);
};
struct {
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[2],31,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp__out_valid[2],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp__in_thread_mask[2],0,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_b_reg_data[2],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_a_reg_data[2],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_write_data[2],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src2_fwd_data[2],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src1_fwd_data[2],31,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_valid[2],0,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[32],31,0);
};
static VL_ST_SIG8(__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[8],4,0);
// INTERNAL VARIABLES

BIN
rtl/obj_dir/VVortex__ALL.a
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rtl/obj_dir/VVortex__ALLcls.o
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2
rtl/obj_dir/VVortex__ver.d
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@@ -1 +1 @@
obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/Cellar/verilator/4.010/bin/verilator_bin /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_alu.v VX_csr_handler.v VX_d_e_reg.v VX_decode.v VX_define.v VX_e_m_reg.v VX_execute.v VX_f_d_reg.v VX_fetch.v VX_forwarding.v VX_m_w_reg.v VX_memory.v VX_register_file.v VX_register_file_slave.v VX_warp.v VX_writeback.v Vortex.v
obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/Cellar/verilator/4.010/bin/verilator_bin /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_alu.v VX_context.v VX_csr_handler.v VX_d_e_reg.v VX_decode.v VX_define.v VX_e_m_reg.v VX_execute.v VX_f_d_reg.v VX_fetch.v VX_forwarding.v VX_m_w_reg.v VX_memory.v VX_register_file.v VX_register_file_slave.v VX_warp.v VX_writeback.v Vortex.v

25
rtl/obj_dir/VVortex__verFiles.dat
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@@ -2,27 +2,28 @@
C "-Wall -cc Vortex.v --exe test_bench.cpp"
S 4608404 12889046060 1553037052 0 1548678579 0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin"
S 2785 12889457986 1554064009 0 1554064009 0 "VX_alu.v"
S 3192 12890338917 1557297615 0 1557297615 0 "VX_context.v"
S 1495 12889457987 1554023089 0 1554023089 0 "VX_csr_handler.v"
S 5105 12889457988 1554023089 0 1554023089 0 "VX_d_e_reg.v"
S 15170 12890307904 1557104321 0 1557104321 0 "VX_decode.v"
S 1557 12890307906 1557104321 0 1557104321 0 "VX_define.v"
S 11838 12890307904 1557297599 0 1557297599 0 "VX_decode.v"
S 1557 12890307906 1557297794 0 1557297794 0 "VX_define.v"
S 4077 12889457992 1554023089 0 1554023089 0 "VX_e_m_reg.v"
S 3288 12889457993 1554023938 0 1554023938 0 "VX_execute.v"
S 1558 12889457994 1554064040 0 1554064040 0 "VX_f_d_reg.v"
S 2237 12890309989 1557111275 0 1557111275 0 "VX_fetch.v"
S 1816 12890309989 1557267615 0 1557267615 0 "VX_fetch.v"
S 5632 12889457996 1554023089 0 1554023089 0 "VX_forwarding.v"
S 1677 12889457997 1554023089 0 1554023089 0 "VX_m_w_reg.v"
S 3732 12890309990 1557110604 0 1557110604 0 "VX_memory.v"
S 1078 12889457999 1554023928 0 1554023928 0 "VX_register_file.v"
S 1387 12889458000 1554023933 0 1554023933 0 "VX_register_file_slave.v"
S 744 12890308905 1557110557 0 1557110557 0 "VX_warp.v"
S 1499 12890308905 1557267602 0 1557267602 0 "VX_warp.v"
S 1454 12890307909 1557104321 0 1557104321 0 "VX_writeback.v"
S 16949 12890307910 1557104321 0 1557104321 0 "Vortex.v"
T 145644 12890311152 1557111277 0 1557111277 0 "obj_dir/VVortex.cpp"
T 14410 12890311151 1557111277 0 1557111277 0 "obj_dir/VVortex.h"
T 1800 12890311154 1557111277 0 1557111277 0 "obj_dir/VVortex.mk"
T 530 12890311150 1557111277 0 1557111277 0 "obj_dir/VVortex__Syms.cpp"
T 711 12890311149 1557111277 0 1557111277 0 "obj_dir/VVortex__Syms.h"
T 499 12890311155 1557111277 0 1557111277 0 "obj_dir/VVortex__ver.d"
T 0 0 1557111277 0 1557111277 0 "obj_dir/VVortex__verFiles.dat"
T 1159 12890311153 1557111277 0 1557111277 0 "obj_dir/VVortex_classes.mk"
T 272889 12890339974 1557297809 0 1557297809 0 "obj_dir/VVortex.cpp"
T 16351 12890339973 1557297809 0 1557297809 0 "obj_dir/VVortex.h"
T 1800 12890339976 1557297809 0 1557297809 0 "obj_dir/VVortex.mk"
T 530 12890339972 1557297809 0 1557297809 0 "obj_dir/VVortex__Syms.cpp"
T 711 12890339971 1557297809 0 1557297809 0 "obj_dir/VVortex__Syms.h"
T 512 12890339977 1557297809 0 1557297809 0 "obj_dir/VVortex__ver.d"
T 0 0 1557297809 0 1557297809 0 "obj_dir/VVortex__verFiles.dat"
T 1159 12890339975 1557297809 0 1557297809 0 "obj_dir/VVortex_classes.mk"

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6
rtl/results.txt
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@@ -1,7 +1,7 @@
# Dynamic Instructions: 149108
# of total cycles: 149120
# Dynamic Instructions: 122612
# of total cycles: 122624
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.00008
# CPI: 1.0001
# time to simulate: 6.95313e-310 milliseconds
# GRADE: Failed on test: 0