381 lines
13 KiB
Systemverilog
381 lines
13 KiB
Systemverilog
`ifndef VX_DEFINE
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`define VX_DEFINE
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`include "VX_config.vh"
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// `define QUEUE_FORCE_MLAB 1
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// `define SYN 1
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// `define ASIC 1
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// `define SYN_FUNC 1
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///////////////////////////////////////////////////////////////////////////////
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`ifndef NDEBUG
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`define DEBUG_BLOCK(x) /* verilator lint_off UNUSED */ \
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x \
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/* verilator lint_on UNUSED */
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`else
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`define DEBUG_BLOCK(x)
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`endif
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`define DEBUG_BEGIN /* verilator lint_off UNUSED */
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`define DEBUG_END /* verilator lint_on UNUSED */
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`define IGNORE_WARNINGS_BEGIN /* verilator lint_off UNUSED */ \
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/* verilator lint_off PINCONNECTEMPTY */ \
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/* verilator lint_off DECLFILENAME */
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`define IGNORE_WARNINGS_END /* verilator lint_on UNUSED */ \
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/* verilator lint_on PINCONNECTEMPTY */ \
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/* verilator lint_on DECLFILENAME */
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`define UNUSED_VAR(x) /* verilator lint_off UNUSED */ \
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wire [$bits(x)-1:0] __``x``__ = x; \
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/* verilator lint_on UNUSED */
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`define UNUSED_PIN(x) /* verilator lint_off PINCONNECTEMPTY */ \
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. x () \
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/* verilator lint_on PINCONNECTEMPTY */
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`define STRINGIFY(x) `"x`"
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`define STATIC_ASSERT(cond, msg) \
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generate \
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if (!(cond)) $error(msg); \
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endgenerate
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`define CLOG2(x) $clog2(x)
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`define FLOG2(x) ($clog2(x) - (((1 << $clog2(x)) > (x)) ? 1 : 0))
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`define LOG2UP(x) (((x) > 1) ? $clog2(x) : 1)
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`define ISPOW2(x) (((x) != 0) && (0 == ((x) & ((x) - 1))))
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`define MIN(x, y) ((x < y) ? (x) : (y))
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`define MAX(x, y) ((x > y) ? (x) : (y))
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`define UP(x) (((x) > 0) ? x : 1)
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///////////////////////////////////////////////////////////////////////////////
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`define NW_BITS `LOG2UP(`NUM_WARPS)
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`define NT_BITS `LOG2UP(`NUM_THREADS)
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`define NC_BITS `LOG2UP(`NUM_CORES)
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`define REQS_BITS `LOG2UP(NUM_REQUESTS)
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`define NUM_GPRS 32
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`define CSR_ADDR_SIZE 12
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`define CSR_WIDTH 12
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///////////////////////////////////////////////////////////////////////////////
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`define BYTE_EN_NO 3'h7
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`define BYTE_EN_SB 3'h0
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`define BYTE_EN_SH 3'h1
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`define BYTE_EN_SW 3'h2
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`define BYTE_EN_UB 3'h4
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`define BYTE_EN_UH 3'h5
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`define BYTE_EN_BITS 3
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///////////////////////////////////////////////////////////////////////////////
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`define INST_R 7'd051
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`define INST_L 7'd003
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`define INST_ALU 7'd019
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`define INST_S 7'd035
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`define INST_B 7'd099
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`define INST_LUI 7'd055
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`define INST_AUIPC 7'd023
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`define INST_JAL 7'd111
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`define INST_JALR 7'd103
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`define INST_SYS 7'd115
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`define INST_GPGPU 7'd107
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`define RS2_IMMED 1
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`define RS2_REG 0
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`define BR_NO 3'h0
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`define BR_EQ 3'h1
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`define BR_NE 3'h2
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`define BR_LT 3'h3
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`define BR_GT 3'h4
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`define BR_LTU 3'h5
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`define BR_GTU 3'h6
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`define ALU_NO 5'd15
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`define ALU_ADD 5'd00
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`define ALU_SUB 5'd01
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`define ALU_SLLA 5'd02
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`define ALU_SLT 5'd03
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`define ALU_SLTU 5'd04
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`define ALU_XOR 5'd05
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`define ALU_SRL 5'd06
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`define ALU_SRA 5'd07
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`define ALU_OR 5'd08
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`define ALU_AND 5'd09
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`define ALU_SUBU 5'd10
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`define ALU_LUI 5'd11
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`define ALU_AUIPC 5'd12
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`define ALU_CSR_RW 5'd13
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`define ALU_CSR_RS 5'd14
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`define ALU_CSR_RC 5'd15
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`define ALU_MUL 5'd16
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`define ALU_MULH 5'd17
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`define ALU_MULHSU 5'd18
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`define ALU_MULHU 5'd19
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`define ALU_DIV 5'd20
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`define ALU_DIVU 5'd21
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`define ALU_REM 5'd22
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`define ALU_REMU 5'd23
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`define WB_NO 2'h0
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`define WB_ALU 2'h1
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`define WB_MEM 2'h2
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`define WB_JAL 2'h3
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///////////////////////////////////////////////////////////////////////////////
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`ifndef NDEBUG // pc, wb, rd, warp_num
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`define DEBUG_CORE_REQ_MDATA_WIDTH (32 + 2 + 5 + `NW_BITS)
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`else
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`define DEBUG_CORE_REQ_MDATA_WIDTH 0
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`endif
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////////////////////////// Dcache Configurable Knobs //////////////////////////
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// Cache ID
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`define DCACHE_ID (((`L3_ENABLE && `L2_ENABLE) ? 2 : `L2_ENABLE ? 1 : 0) + (CORE_ID * 3) + 0)
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// TAG sharing enable
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`define DCORE_TAG_ID_BITS `LOG2UP(`DCREQ_SIZE)
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// Core request tag bits
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`define DCORE_TAG_WIDTH (`DEBUG_CORE_REQ_MDATA_WIDTH + `DCORE_TAG_ID_BITS)
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// DRAM request data bits
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`define DDRAM_LINE_WIDTH (`DBANK_LINE_SIZE * 8)
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// DRAM request address bits
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`define DDRAM_ADDR_WIDTH (32 - `CLOG2(`DBANK_LINE_SIZE))
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// DRAM byte enable bits
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`define DDRAM_BYTEEN_WIDTH `DBANK_LINE_SIZE
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// DRAM request tag bits
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`define DDRAM_TAG_WIDTH `DDRAM_ADDR_WIDTH
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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`define DNUM_REQUESTS `NUM_THREADS
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// Snoop request tag bits
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`define DSNP_TAG_WIDTH ((`NUM_CORES > 1) ? `LOG2UP(`L2SNRQ_SIZE) : `L2SNP_TAG_WIDTH)
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////////////////////////// Icache Configurable Knobs //////////////////////////
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// Cache ID
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`define ICACHE_ID (((`L3_ENABLE && `L2_ENABLE) ? 2 : `L2_ENABLE ? 1 : 0) + (CORE_ID * 3) + 1)
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// Core request address bits
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`define ICORE_ADDR_WIDTH (32-`CLOG2(`IWORD_SIZE))
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// Core request byte enable bits
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`define ICORE_BYTEEN_WIDTH `DWORD_SIZE
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// TAG sharing enable
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`define ICORE_TAG_ID_BITS `LOG2UP(`ICREQ_SIZE)
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// Core request tag bits
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`define ICORE_TAG_WIDTH (`DEBUG_CORE_REQ_MDATA_WIDTH + `ICORE_TAG_ID_BITS)
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// DRAM request data bits
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`define IDRAM_LINE_WIDTH (`IBANK_LINE_SIZE * 8)
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// DRAM request address bits
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`define IDRAM_ADDR_WIDTH (32 - `CLOG2(`IBANK_LINE_SIZE))
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// DRAM byte enable bits
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`define IDRAM_BYTEEN_WIDTH `IBANK_LINE_SIZE
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// DRAM request tag bits
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`define IDRAM_TAG_WIDTH `IDRAM_ADDR_WIDTH
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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`define INUM_REQUESTS 1
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////////////////////////// SM Configurable Knobs //////////////////////////////
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// Cache ID
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`define SCACHE_ID (((`L3_ENABLE && `L2_ENABLE) ? 2 : `L2_ENABLE ? 1 : 0) + (CORE_ID * 3) + 3)
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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`define SNUM_REQUESTS `NUM_THREADS
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// DRAM request address bits
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`define SDRAM_ADDR_WIDTH (32 - `CLOG2(`SBANK_LINE_SIZE))
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// DRAM request tag bits
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`define SDRAM_TAG_WIDTH `SDRAM_ADDR_WIDTH
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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`define SNUM_REQUESTS `NUM_THREADS
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////////////////////////// L2cache Configurable Knobs /////////////////////////
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// Cache ID
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`define L2CACHE_ID (`L3_ENABLE ? 1 : 0)
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// DRAM request data bits
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`define L2DRAM_LINE_WIDTH (`L2_ENABLE ? (`L2BANK_LINE_SIZE * 8) : `DDRAM_LINE_WIDTH)
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// DRAM request address bits
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`define L2DRAM_ADDR_WIDTH (`L2_ENABLE ? (32 - `CLOG2(`L2BANK_LINE_SIZE)) : `DDRAM_ADDR_WIDTH)
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// DRAM byte enable bits
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`define L2DRAM_BYTEEN_WIDTH (`L2_ENABLE ? `L2BANK_LINE_SIZE : `DDRAM_BYTEEN_WIDTH)
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// DRAM request tag bits
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`define L2DRAM_TAG_WIDTH (`L2_ENABLE ? `L2DRAM_ADDR_WIDTH : (`L2DRAM_ADDR_WIDTH+`CLOG2(`NUM_CORES*2)))
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// Snoop request tag bits
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`define L2SNP_TAG_WIDTH (`L3_ENABLE ? `LOG2UP(`L3SNRQ_SIZE) : `L3SNP_TAG_WIDTH)
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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`define L2NUM_REQUESTS (2 * `NUM_CORES)
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////////////////////////// L3cache Configurable Knobs /////////////////////////
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// Cache ID
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`define L3CACHE_ID 0
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// DRAM request data bits
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`define L3DRAM_LINE_WIDTH (`L3_ENABLE ? (`L3BANK_LINE_SIZE * 8) : `L2DRAM_LINE_WIDTH)
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// DRAM request address bits
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`define L3DRAM_ADDR_WIDTH (`L3_ENABLE ? (32 - `CLOG2(`L3BANK_LINE_SIZE)) : `L2DRAM_ADDR_WIDTH)
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// DRAM byte enable bits
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`define L3DRAM_BYTEEN_WIDTH (`L3_ENABLE ? `L3BANK_LINE_SIZE : `L2DRAM_BYTEEN_WIDTH)
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// DRAM request tag bits
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`define L3DRAM_TAG_WIDTH (`L3_ENABLE ? `L3DRAM_ADDR_WIDTH : `L2DRAM_TAG_WIDTH)
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// Snoop request tag bits
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`define L3SNP_TAG_WIDTH 16
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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`define L3NUM_REQUESTS `NUM_CLUSTERS
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///////////////////////////////////////////////////////////////////////////////
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`define VX_DRAM_BYTEEN_WIDTH `L3DRAM_BYTEEN_WIDTH
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`define VX_DRAM_ADDR_WIDTH `L3DRAM_ADDR_WIDTH
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`define VX_DRAM_LINE_WIDTH `L3DRAM_LINE_WIDTH
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`define VX_DRAM_TAG_WIDTH `L3DRAM_TAG_WIDTH
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`define VX_SNP_TAG_WIDTH `L3SNP_TAG_WIDTH
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`define VX_CORE_TAG_WIDTH `DCORE_TAG_WIDTH
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`define DRAM_TO_BYTE_ADDR(x) {x, (32-$bits(x))'(0)}
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///////////////////////////////////////////////////////////////////////////////
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`ifdef SCOPE
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`define SCOPE_SIGNALS_LIST() \
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scope_icache_req_valid, \
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scope_icache_req_tag, \
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scope_icache_req_ready, \
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scope_icache_rsp_valid, \
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scope_icache_rsp_tag, \
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scope_icache_rsp_ready, \
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scope_dcache_req_valid, \
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scope_dcache_req_tag, \
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scope_dcache_req_ready, \
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scope_dcache_rsp_valid, \
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scope_dcache_rsp_tag, \
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scope_dcache_rsp_ready, \
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scope_dram_req_valid, \
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scope_dram_req_tag, \
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scope_dram_req_ready, \
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scope_dram_rsp_valid, \
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scope_dram_rsp_tag, \
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scope_dram_rsp_ready, \
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scope_schedule_delay
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`define SCOPE_SIGNALS_DECL() \
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wire scope_icache_req_valid; \
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wire [`DCORE_TAG_WIDTH-1:0] scope_icache_req_tag; \
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wire scope_icache_req_ready; \
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wire scope_icache_rsp_valid; \
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wire [`DCORE_TAG_WIDTH-1:0] scope_icache_rsp_tag; \
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wire scope_icache_rsp_ready; \
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wire [`DNUM_REQUESTS-1:0] scope_dcache_req_valid; \
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wire [`ICORE_TAG_WIDTH-1:0] scope_dcache_req_tag; \
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wire scope_dcache_req_ready; \
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wire [`DNUM_REQUESTS-1:0] scope_dcache_rsp_valid; \
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wire [`ICORE_TAG_WIDTH-1:0] scope_dcache_rsp_tag; \
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wire scope_dcache_rsp_ready; \
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wire scope_dram_req_valid; \
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wire [`VX_DRAM_TAG_WIDTH-1:0] scope_dram_req_tag; \
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wire scope_dram_req_ready; \
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wire scope_dram_rsp_valid; \
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wire [`VX_DRAM_TAG_WIDTH-1:0] scope_dram_rsp_tag; \
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wire scope_dram_rsp_ready; \
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wire scope_schedule_delay;
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`define SCOPE_SIGNALS_IO() \
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/* verilator lint_off UNDRIVEN */ \
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output wire scope_icache_req_valid, \
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output wire [`DCORE_TAG_WIDTH-1:0] scope_icache_req_tag, \
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output wire scope_icache_req_ready, \
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output wire scope_icache_rsp_valid, \
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output wire [`DCORE_TAG_WIDTH-1:0] scope_icache_rsp_tag, \
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output wire scope_icache_rsp_ready, \
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output wire [`DNUM_REQUESTS-1:0] scope_dcache_req_valid, \
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output wire [`ICORE_TAG_WIDTH-1:0] scope_dcache_req_tag, \
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output wire scope_dcache_req_ready, \
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output wire [`DNUM_REQUESTS-1:0] scope_dcache_rsp_valid, \
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output wire [`ICORE_TAG_WIDTH-1:0] scope_dcache_rsp_tag, \
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output wire scope_dcache_rsp_ready, \
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output wire scope_dram_req_valid, \
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output wire [`VX_DRAM_TAG_WIDTH-1:0] scope_dram_req_tag, \
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output wire scope_dram_req_ready, \
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output wire scope_dram_rsp_valid, \
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output wire [`VX_DRAM_TAG_WIDTH-1:0] scope_dram_rsp_tag, \
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output wire scope_dram_rsp_ready, \
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output wire scope_schedule_delay \
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/* verilator lint_on UNDRIVEN */
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`define SCOPE_SIGNALS_ATTACH() \
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.scope_icache_req_valid (scope_icache_req_valid), \
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.scope_icache_req_tag (scope_icache_req_tag), \
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.scope_icache_req_ready (scope_icache_req_ready), \
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.scope_icache_rsp_valid (scope_icache_rsp_valid), \
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.scope_icache_rsp_tag (scope_icache_rsp_tag), \
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.scope_icache_rsp_ready (scope_icache_rsp_ready), \
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.scope_dcache_req_valid (scope_dcache_req_valid), \
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.scope_dcache_req_tag (scope_dcache_req_tag), \
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.scope_dcache_req_ready (scope_dcache_req_ready), \
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.scope_dcache_rsp_valid (scope_dcache_rsp_valid), \
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.scope_dcache_rsp_tag (scope_dcache_rsp_tag), \
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.scope_dcache_rsp_ready (scope_dcache_rsp_ready), \
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.scope_dram_req_valid (scope_dram_req_valid), \
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.scope_dram_req_tag (scope_dram_req_tag), \
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.scope_dram_req_ready (scope_dram_req_ready), \
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.scope_dram_rsp_valid (scope_dram_rsp_valid), \
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.scope_dram_rsp_tag (scope_dram_rsp_tag), \
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.scope_dram_rsp_ready (scope_dram_rsp_ready), \
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.scope_schedule_delay (scope_schedule_delay)
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`define SCOPE_ASSIGN(d,s) assign d = s
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`else
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`define SCOPE_SIGNALS_IO()
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`define SCOPE_SIGNALS_ATTACH()
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`define SCOPE_ASSIGN(d,s)
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`endif
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// VX_DEFINE
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`endif
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