d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
70 lines
2.2 KiB
Markdown
70 lines
2.2 KiB
Markdown
# Vortex Cache Subsystem
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The Vortex Cache Sub-system has the following main properties:
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- High-bandwidth with bank parallelism
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- Snoop protocol to flush data for CPU access
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- Generic design: Dcache, Icache, Shared Memory, L2 cache, L3 cache
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### Cache Hierarchy
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- Cache can be configured to be any level in the hierarchy
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- Caches communicate via snooping
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- Cache flush from AFU is passed down the hierarchy
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### VX_cache.v (Top Module)
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VX.cache.v is the top module of the cache verilog code located in the `/hw/rtl/cache` directory.
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- Configurable (Cache size, number of banks, bank line size, etc.)
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- I/O signals
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- Core Request
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- Core Rsp
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- DRAM Req
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- DRAM Rsp
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- Snoop Rsp
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- Snoop Rsp
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- Snoop Forwarding Out
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- Snoop Forwarding In
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- Bank Select
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- Assigns valid and ready signals for each bank
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- Snoop Forwarder
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- DRAM Request Arbiter
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- Prepares cache response for communication with DRAM
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- Snoop Response Arbiter
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- Sends snoop response
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- Core Response Merge
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- Cache accesses one line at a time. As a result, each request may not come back in the same response. This module tries to recombine the responses by thread ID.
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### VX_cache_bank.v
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VX_cache_bank.v is the verilog code that handles cache bank functionality and is located in the `/hw/rtl/cache` directory.
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- Allows for high throughput
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- Each bank contains queues to hold requests to the cache
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- I/O signals
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- Core request
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- Core Response
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- DRAM Fill Requests
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- DRAM Fill Response
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- DRAM WB Requests
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- Snp Request
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- Snp Response
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- Request Priority: DRAM fill, miss reserve, core request, snoop request
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- Snoop Request Queue
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- DRAM Fill Queue
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- Core Req Arbiter
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- Requests to be processed by the bank
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- Tag Data Store
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- Registers for valid, dirty, dirtyb, tag, and data
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- Length of registers determined by lines in the bank
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- Tag Data Access:
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- I/O: stall, snoop info, force request miss
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- Writes to cache or sends read response; hit or miss determined here
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- A missed request goes to the miss reserve if it is not a snoop request or DRAM fill |