d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
156 lines
4.6 KiB
Systemverilog
156 lines
4.6 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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module VX_cluster import VX_gpu_pkg::*; #(
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parameter CLUSTER_ID = 0
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) (
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`SCOPE_IO_DECL
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// Clock
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input wire clk,
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input wire reset,
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`ifdef PERF_ENABLE
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VX_mem_perf_if.master mem_perf_if,
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VX_mem_perf_if.slave perf_memsys_total_if,
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`endif
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VX_dcr_bus_if.slave dcr_bus_if,
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// Memory
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VX_mem_bus_if.master mem_bus_if,
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// simulation helper signals
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output wire sim_ebreak,
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output wire [`NUM_REGS-1:0][`XLEN-1:0] sim_wb_value,
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// Status
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output wire busy
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);
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`ifdef SCOPE
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localparam scope_socket = 0;
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`SCOPE_IO_SWITCH (scope_socket + `NUM_SOCKETS);
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`endif
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`ifdef GBAR_ENABLE
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VX_gbar_bus_if per_socket_gbar_bus_if[`NUM_SOCKETS]();
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VX_gbar_bus_if gbar_bus_if();
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`RESET_RELAY (gbar_reset, reset);
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VX_gbar_arb #(
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.NUM_REQS (`NUM_SOCKETS),
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.OUT_REG ((`NUM_SOCKETS > 2) ? 1 : 0) // bgar_unit has no backpressure
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) gbar_arb (
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.clk (clk),
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.reset (gbar_reset),
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.bus_in_if (per_socket_gbar_bus_if),
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.bus_out_if (gbar_bus_if)
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);
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VX_gbar_unit #(
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.INSTANCE_ID ($sformatf("gbar%0d", CLUSTER_ID))
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) gbar_unit (
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.clk (clk),
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.reset (gbar_reset),
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.gbar_bus_if (gbar_bus_if)
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);
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`endif
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VX_mem_bus_if #(
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.DATA_SIZE (DCACHE_WORD_SIZE),
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.TAG_WIDTH (DCACHE_ARB_TAG_WIDTH)
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) per_socket_dcache_bus_if[`NUM_SOCKETS * DCACHE_NUM_REQS]();
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VX_mem_bus_if #(
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.DATA_SIZE (ICACHE_WORD_SIZE),
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.TAG_WIDTH (ICACHE_ARB_TAG_WIDTH)
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) per_socket_icache_bus_if[`NUM_SOCKETS]();
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`RESET_RELAY (mem_unit_reset, reset);
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VX_mem_unit #(
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.CLUSTER_ID (CLUSTER_ID)
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) mem_unit (
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.clk (clk),
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.reset (mem_unit_reset),
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`ifdef PERF_ENABLE
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.mem_perf_if (mem_perf_if),
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`endif
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.dcache_bus_if (per_socket_dcache_bus_if),
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.icache_bus_if (per_socket_icache_bus_if),
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.mem_bus_if (mem_bus_if)
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);
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///////////////////////////////////////////////////////////////////////////
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wire [`NUM_SOCKETS-1:0] per_socket_sim_ebreak;
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wire [`NUM_SOCKETS-1:0][`NUM_REGS-1:0][`XLEN-1:0] per_socket_sim_wb_value;
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assign sim_ebreak = per_socket_sim_ebreak[0];
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assign sim_wb_value = per_socket_sim_wb_value[0];
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`UNUSED_VAR (per_socket_sim_ebreak)
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`UNUSED_VAR (per_socket_sim_wb_value)
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VX_dcr_bus_if socket_dcr_bus_tmp_if();
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assign socket_dcr_bus_tmp_if.write_valid = dcr_bus_if.write_valid && (dcr_bus_if.write_addr >= `VX_DCR_BASE_STATE_BEGIN && dcr_bus_if.write_addr < `VX_DCR_BASE_STATE_END);
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assign socket_dcr_bus_tmp_if.write_addr = dcr_bus_if.write_addr;
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assign socket_dcr_bus_tmp_if.write_data = dcr_bus_if.write_data;
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wire [`NUM_SOCKETS-1:0] per_socket_busy;
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`BUFFER_DCR_BUS_IF (socket_dcr_bus_if, socket_dcr_bus_tmp_if, (`NUM_SOCKETS > 1));
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// Generate all sockets
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for (genvar i = 0; i < `NUM_SOCKETS; ++i) begin
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`RESET_RELAY (socket_reset, reset);
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VX_socket #(
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.SOCKET_ID ((CLUSTER_ID * `NUM_SOCKETS) + i)
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) socket (
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`SCOPE_IO_BIND (scope_socket+i)
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.clk (clk),
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.reset (socket_reset),
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`ifdef PERF_ENABLE
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.mem_perf_if (perf_memsys_total_if),
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`endif
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.dcr_bus_if (socket_dcr_bus_if),
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.dcache_bus_if (per_socket_dcache_bus_if[i * DCACHE_NUM_REQS +: DCACHE_NUM_REQS]),
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.icache_bus_if (per_socket_icache_bus_if[i]),
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`ifdef GBAR_ENABLE
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.gbar_bus_if (per_socket_gbar_bus_if[i]),
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`endif
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.sim_ebreak (per_socket_sim_ebreak[i]),
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.sim_wb_value (per_socket_sim_wb_value[i]),
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.busy (per_socket_busy[i])
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);
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end
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`BUFFER_BUSY (busy, (| per_socket_busy), (`NUM_SOCKETS > 1));
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endmodule
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