591 lines
18 KiB
Verilog
591 lines
18 KiB
Verilog
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`include "VX_define.v"
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module Vortex(
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input wire clk,
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input wire reset,
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input wire[31:0] fe_instruction,
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// input wire[31:0] in_cache_driver_out_data_0,
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// input wire[31:0] in_cache_driver_out_data_1,
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input wire[31:0] in_cache_driver_out_data[`NT_M1:0],
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output wire[31:0] curr_PC,
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output wire[31:0] out_cache_driver_in_address[`NT_M1:0],
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output wire[2:0] out_cache_driver_in_mem_read,
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output wire[2:0] out_cache_driver_in_mem_write,
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output wire out_cache_driver_in_valid[`NT_M1:0],
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output wire[31:0] out_cache_driver_in_data[`NT_M1:0],
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output wire out_ebreak
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);
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// wire[31:0] in_cache_driver_out_data[`NT_M1:0];
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// assign in_cache_driver_out_data[0] = in_cache_driver_out_data_0;
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// assign in_cache_driver_out_data[1] = in_cache_driver_out_data_1;
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assign curr_PC = fetch_curr_PC;
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// From fetch
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wire[31:0] fetch_instruction;
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wire fetch_delay;
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wire[31:0] fetch_curr_PC;
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wire fetch_valid[`NT_M1:0];
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wire[`NW_M1:0] fetch_warp_num;
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wire fetch_ebreak;
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wire[`NW_M1:0] fetch_which_warp;
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// From f_d_register
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wire[31:0] f_d_instruction;
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wire[31:0] f_d_curr_PC;
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wire f_d_valid[`NT_M1:0];
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wire[`NW_M1:0] f_d_warp_num;
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// From decode
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wire decode_branch_stall;
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wire[11:0] decode_csr_address;
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wire decode_is_csr;
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wire[31:0] decode_csr_mask;
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wire[4:0] decode_rd;
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wire[4:0] decode_rs1;
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wire[4:0] decode_rs2;
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wire[31:0] decode_a_reg_data[`NT_M1:0];
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wire[31:0] decode_b_reg_data[`NT_M1:0];
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wire[1:0] decode_wb;
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wire[4:0] decode_alu_op;
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wire decode_rs2_src;
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reg[31:0] decode_itype_immed;
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wire[2:0] decode_mem_read;
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wire[2:0] decode_mem_write;
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reg[2:0] decode_branch_type;
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reg decode_jal;
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reg[31:0] decode_jal_offset;
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reg[19:0] decode_upper_immed;
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wire[31:0] decode_PC_next;
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wire decode_valid[`NT_M1:0];
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wire decode_clone_stall;
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wire decode_change_mask;
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wire decode_thread_mask[`NT_M1:0];
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wire[`NW_M1:0] decode_warp_num;
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wire decode_wspawn;
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wire[31:0] decode_wspawn_pc;
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wire decode_ebreak;
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// From d_e_register
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wire[11:0] d_e_csr_address;
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wire d_e_is_csr;
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wire[31:0] d_e_csr_mask;
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wire[4:0] d_e_rd;
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wire[4:0] d_e_rs1;
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wire[4:0] d_e_rs2;
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wire[31:0] d_e_a_reg_data[`NT_M1:0];
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wire[31:0] d_e_b_reg_data[`NT_M1:0];
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wire[4:0] d_e_alu_op;
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wire[1:0] d_e_wb;
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wire d_e_rs2_src;
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wire[31:0] d_e_itype_immed;
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wire[2:0] d_e_mem_read;
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wire[2:0] d_e_mem_write;
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wire[2:0] d_e_branch_type;
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wire[19:0] d_e_upper_immed;
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wire[31:0] d_e_curr_PC;
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wire d_e_jal;
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wire[31:0] d_e_jal_offset;
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wire[31:0] d_e_PC_next;
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wire d_e_valid[`NT_M1:0];
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wire[`NW_M1:0] d_e_warp_num;
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// From execute
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wire execute_branch_stall;
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wire[11:0] execute_csr_address;
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wire execute_is_csr;
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reg[31:0] execute_csr_result;
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reg[31:0] execute_alu_result[`NT_M1:0];
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wire[4:0] execute_rd;
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wire[1:0] execute_wb;
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wire[4:0] execute_rs1;
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wire[4:0] execute_rs2;
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wire[31:0] execute_a_reg_data[`NT_M1:0];
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wire[31:0] execute_b_reg_data[`NT_M1:0];
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wire[2:0] execute_mem_read;
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wire[2:0] execute_mem_write;
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wire execute_jal;
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wire[31:0] execute_jal_dest;
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wire[31:0] execute_branch_offset;
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wire[31:0] execute_PC_next;
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wire execute_valid[`NT_M1:0];
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wire[`NW_M1:0] execute_warp_num;
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// From e_m_register
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wire e_m_jal;
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wire[31:0] e_m_jal_dest;
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wire[11:0] e_m_csr_address;
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wire e_m_is_csr;
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wire[31:0] e_m_csr_result;
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wire[31:0] e_m_alu_result[`NT_M1:0];
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wire[4:0] e_m_rd;
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wire[1:0] e_m_wb;
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wire[4:0] e_m_rs1;
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/* verilator lint_off UNUSED */
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wire[31:0] e_m_a_reg_data[`NT_M1:0];
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/* verilator lint_on UNUSED */
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wire[31:0] e_m_b_reg_data[`NT_M1:0];
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wire[4:0] e_m_rs2;
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wire[2:0] e_m_mem_read;
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wire[2:0] e_m_mem_write;
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wire[31:0] e_m_curr_PC;
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wire[31:0] e_m_branch_offset;
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wire[2:0] e_m_branch_type;
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wire[31:0] e_m_PC_next;
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wire e_m_valid[`NT_M1:0];
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wire[`NW_M1:0] e_m_warp_num;
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// From memory
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wire memory_delay;
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wire memory_branch_dir;
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wire[31:0] memory_branch_dest;
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wire[31:0] memory_alu_result[`NT_M1:0];
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wire[31:0] memory_mem_result[`NT_M1:0];
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wire[4:0] memory_rd;
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wire[1:0] memory_wb;
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wire[4:0] memory_rs1;
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wire[4:0] memory_rs2;
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wire[31:0] memory_PC_next;
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wire memory_valid[`NT_M1:0];
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wire[`NW_M1:0] memory_warp_num;
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// From m_w_register
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wire[31:0] m_w_alu_result[`NT_M1:0];
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wire[31:0] m_w_mem_result[`NT_M1:0];
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wire[4:0] m_w_rd;
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wire[1:0] m_w_wb;
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/* verilator lint_off UNUSED */
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wire[4:0] m_w_rs1;
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wire[4:0] m_w_rs2;
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/* verilator lint_on UNUSED */
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wire[31:0] m_w_PC_next;
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wire m_w_valid[`NT_M1:0];
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wire[`NW_M1:0] m_w_warp_num;
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// From writeback
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wire[31:0] writeback_write_data[`NT_M1:0];
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wire[4:0] writeback_rd;
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wire[1:0] writeback_wb;
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wire[`NW_M1:0] writeback_warp_num;
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// From csr handler
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wire[31:0] csr_decode_csr_data;
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// From forwarding
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wire forwarding_fwd_stall;
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wire forwarding_src1_fwd;
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wire forwarding_src2_fwd;
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/* verilator lint_off UNUSED */
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wire forwarding_csr_fwd;
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wire[31:0] forwarding_csr_fwd_data;
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/* verilator lint_on UNUSED */
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wire[31:0] forwarding_src1_fwd_data[`NT_M1:0];
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wire[31:0] forwarding_src2_fwd_data[`NT_M1:0];
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// Internal
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wire total_freeze;
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wire interrupt;
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wire debug;
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assign debug = 1'b0;
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assign interrupt = 1'b0;
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assign total_freeze = fetch_delay || memory_delay;
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assign out_ebreak = fetch_ebreak;
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VX_fetch vx_fetch(
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.clk (clk),
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.reset (reset),
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.in_branch_dir (memory_branch_dir),
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.in_freeze (total_freeze),
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.in_branch_dest (memory_branch_dest),
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.in_branch_stall (decode_branch_stall),
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.in_fwd_stall (forwarding_fwd_stall),
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.in_branch_stall_exe(execute_branch_stall),
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.in_clone_stall (decode_clone_stall),
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.in_jal (e_m_jal),
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.in_jal_dest (e_m_jal_dest),
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.in_interrupt (interrupt),
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.in_debug (debug),
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.in_instruction (fe_instruction),
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.in_thread_mask (decode_thread_mask),
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.in_change_mask (decode_change_mask),
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.in_decode_warp_num (decode_warp_num),
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.in_memory_warp_num (memory_warp_num),
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.in_wspawn (decode_wspawn),
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.in_wspawn_pc (decode_wspawn_pc),
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.in_ebreak (decode_ebreak),
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.out_instruction (fetch_instruction),
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.out_delay (fetch_delay),
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.out_curr_PC (fetch_curr_PC),
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.out_warp_num (fetch_warp_num),
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.out_valid (fetch_valid),
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.out_ebreak (fetch_ebreak),
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.out_which_wspawn (fetch_which_warp)
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);
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VX_f_d_reg vx_f_d_reg(
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.clk (clk),
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.reset (reset),
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.in_instruction (fetch_instruction),
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.in_valid (fetch_valid),
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.in_curr_PC (fetch_curr_PC),
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.in_fwd_stall (forwarding_fwd_stall),
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.in_freeze (total_freeze),
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.in_clone_stall (decode_clone_stall),
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.in_warp_num (fetch_warp_num),
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.out_instruction(f_d_instruction),
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.out_curr_PC (f_d_curr_PC),
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.out_valid (f_d_valid),
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.out_warp_num (f_d_warp_num)
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);
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VX_decode vx_decode(
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.clk (clk),
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.in_instruction (f_d_instruction),
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.in_curr_PC (f_d_curr_PC),
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.in_valid (f_d_valid),
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.in_write_data (writeback_write_data),
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.in_rd (writeback_rd),
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.in_wb (writeback_wb),
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.in_wb_warp_num (writeback_warp_num),
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.in_wb_valid (m_w_valid),
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.in_src1_fwd (forwarding_src1_fwd),
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.in_src1_fwd_data(forwarding_src1_fwd_data),
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.in_src2_fwd (forwarding_src2_fwd),
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.in_src2_fwd_data(forwarding_src2_fwd_data),
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.in_warp_num (f_d_warp_num),
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.in_which_wspawn (fetch_which_warp),
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.out_csr_address (decode_csr_address),
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.out_is_csr (decode_is_csr),
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.out_csr_mask (decode_csr_mask),
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.out_rd (decode_rd),
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.out_rs1 (decode_rs1),
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.out_rs2 (decode_rs2),
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.out_a_reg_data (decode_a_reg_data),
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.out_b_reg_data (decode_b_reg_data),
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.out_wb (decode_wb),
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.out_alu_op (decode_alu_op),
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.out_rs2_src (decode_rs2_src),
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.out_itype_immed (decode_itype_immed),
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.out_mem_read (decode_mem_read),
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.out_mem_write (decode_mem_write),
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.out_branch_type (decode_branch_type),
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.out_branch_stall(decode_branch_stall),
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.out_jal (decode_jal),
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.out_jal_offset (decode_jal_offset),
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.out_upper_immed (decode_upper_immed),
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.out_PC_next (decode_PC_next),
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.out_valid (decode_valid),
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.out_clone_stall (decode_clone_stall),
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.out_change_mask (decode_change_mask),
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.out_thread_mask (decode_thread_mask),
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.out_warp_num (decode_warp_num),
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.out_wspawn (decode_wspawn),
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.out_wspawn_pc (decode_wspawn_pc),
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.out_ebreak (decode_ebreak)
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);
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VX_d_e_reg vx_d_e_reg(
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.clk (clk),
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.in_rd (decode_rd),
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.in_rs1 (decode_rs1),
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.in_rs2 (decode_rs2),
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.in_a_reg_data (decode_a_reg_data),
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.in_b_reg_data (decode_b_reg_data),
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.in_alu_op (decode_alu_op),
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.in_wb (decode_wb),
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.in_rs2_src (decode_rs2_src),
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.in_itype_immed (decode_itype_immed),
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.in_mem_read (decode_mem_read),
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.in_mem_write (decode_mem_write),
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.in_PC_next (decode_PC_next),
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.in_branch_type (decode_branch_type),
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.in_fwd_stall (forwarding_fwd_stall),
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.in_branch_stall(execute_branch_stall),
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.in_upper_immed (decode_upper_immed),
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.in_csr_address (decode_csr_address),
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.in_is_csr (decode_is_csr),
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.in_csr_mask (decode_csr_mask),
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.in_curr_PC (f_d_curr_PC),
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.in_jal (decode_jal),
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.in_jal_offset (decode_jal_offset),
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.in_freeze (total_freeze),
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.in_valid (decode_valid),
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.in_clone_stall (decode_clone_stall),
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.in_warp_num (decode_warp_num),
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.out_csr_address(d_e_csr_address),
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.out_is_csr (d_e_is_csr),
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.out_csr_mask (d_e_csr_mask),
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.out_rd (d_e_rd),
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.out_rs1 (d_e_rs1),
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.out_rs2 (d_e_rs2),
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.out_a_reg_data (d_e_a_reg_data),
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.out_b_reg_data (d_e_b_reg_data),
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.out_alu_op (d_e_alu_op),
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.out_wb (d_e_wb),
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.out_rs2_src (d_e_rs2_src),
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.out_itype_immed(d_e_itype_immed),
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.out_mem_read (d_e_mem_read),
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.out_mem_write (d_e_mem_write),
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.out_branch_type(d_e_branch_type),
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.out_upper_immed(d_e_upper_immed),
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.out_curr_PC (d_e_curr_PC),
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.out_jal (d_e_jal),
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.out_jal_offset (d_e_jal_offset),
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.out_PC_next (d_e_PC_next),
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.out_valid (d_e_valid),
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.out_warp_num (d_e_warp_num)
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);
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VX_execute vx_execute(
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.in_rd (d_e_rd),
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.in_rs1 (d_e_rs1),
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.in_rs2 (d_e_rs2),
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.in_a_reg_data (d_e_a_reg_data),
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.in_b_reg_data (d_e_b_reg_data),
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.in_alu_op (d_e_alu_op),
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.in_wb (d_e_wb),
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.in_rs2_src (d_e_rs2_src),
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.in_itype_immed (d_e_itype_immed),
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.in_mem_read (d_e_mem_read),
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.in_mem_write (d_e_mem_write),
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.in_PC_next (d_e_PC_next),
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.in_branch_type (d_e_branch_type),
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.in_upper_immed (d_e_upper_immed),
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.in_csr_address (d_e_csr_address),
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.in_is_csr (d_e_is_csr),
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.in_csr_data (csr_decode_csr_data),
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.in_csr_mask (d_e_csr_mask),
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.in_jal (d_e_jal),
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.in_jal_offset (d_e_jal_offset),
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.in_curr_PC (d_e_curr_PC),
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.in_valid (d_e_valid),
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.in_warp_num (d_e_warp_num),
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.out_csr_address (execute_csr_address),
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.out_is_csr (execute_is_csr),
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.out_csr_result (execute_csr_result),
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.out_alu_result (execute_alu_result),
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.out_rd (execute_rd),
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.out_wb (execute_wb),
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.out_rs1 (execute_rs1),
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.out_rs2 (execute_rs2),
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.out_a_reg_data (execute_a_reg_data),
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.out_b_reg_data (execute_b_reg_data),
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.out_mem_read (execute_mem_read),
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.out_mem_write (execute_mem_write),
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.out_jal (execute_jal),
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.out_jal_dest (execute_jal_dest),
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.out_branch_offset(execute_branch_offset),
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.out_branch_stall (execute_branch_stall),
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.out_PC_next (execute_PC_next),
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.out_valid (execute_valid),
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.out_warp_num (execute_warp_num)
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);
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VX_e_m_reg vx_e_m_reg(
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.clk (clk),
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.in_alu_result (execute_alu_result),
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.in_rd (execute_rd),
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.in_wb (execute_wb),
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.in_rs1 (execute_rs1),
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.in_rs2 (execute_rs2),
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.in_a_reg_data (execute_a_reg_data),
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.in_b_reg_data (execute_b_reg_data),
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.in_mem_read (execute_mem_read),
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.in_mem_write (execute_mem_write),
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.in_PC_next (execute_PC_next),
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.in_csr_address (execute_csr_address),
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|
.in_is_csr (execute_is_csr),
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|
.in_csr_result (execute_csr_result),
|
|
.in_curr_PC (d_e_curr_PC),
|
|
.in_branch_offset (execute_branch_offset),
|
|
.in_branch_type (d_e_branch_type),
|
|
.in_jal (execute_jal),
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|
.in_jal_dest (execute_jal_dest),
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|
.in_freeze (total_freeze),
|
|
.in_valid (execute_valid),
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|
.in_warp_num (execute_warp_num),
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|
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.out_csr_address (e_m_csr_address),
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|
.out_is_csr (e_m_is_csr),
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|
.out_csr_result (e_m_csr_result),
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|
.out_alu_result (e_m_alu_result),
|
|
.out_rd (e_m_rd),
|
|
.out_wb (e_m_wb),
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|
.out_rs1 (e_m_rs1),
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|
.out_rs2 (e_m_rs2),
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|
.out_a_reg_data (e_m_a_reg_data),
|
|
.out_b_reg_data (e_m_b_reg_data),
|
|
.out_mem_read (e_m_mem_read),
|
|
.out_mem_write (e_m_mem_write),
|
|
.out_curr_PC (e_m_curr_PC),
|
|
.out_branch_offset(e_m_branch_offset),
|
|
.out_branch_type (e_m_branch_type),
|
|
.out_jal (e_m_jal),
|
|
.out_jal_dest (e_m_jal_dest),
|
|
.out_PC_next (e_m_PC_next),
|
|
.out_valid (e_m_valid),
|
|
.out_warp_num (e_m_warp_num)
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);
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// wire[31:0] use_rd2[`NT_M1:0];
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// assign use_rd2[0] = e_m_reg_data[1];
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// assign use_rd2[1] = e_m_reg_data[3];
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VX_memory vx_memory(
|
|
.clk (clk),
|
|
.in_alu_result (e_m_alu_result),
|
|
.in_mem_read (e_m_mem_read),
|
|
.in_mem_write (e_m_mem_write),
|
|
.in_rd (e_m_rd),
|
|
.in_wb (e_m_wb),
|
|
.in_rs1 (e_m_rs1),
|
|
.in_rs2 (e_m_rs2),
|
|
.in_rd2 (e_m_b_reg_data),
|
|
.in_PC_next (e_m_PC_next),
|
|
.in_curr_PC (e_m_curr_PC),
|
|
.in_branch_offset (e_m_branch_offset),
|
|
.in_branch_type (e_m_branch_type),
|
|
.in_valid (e_m_valid),
|
|
.in_cache_driver_out_data (in_cache_driver_out_data),
|
|
.in_warp_num (e_m_warp_num),
|
|
|
|
.out_alu_result (memory_alu_result),
|
|
.out_mem_result (memory_mem_result),
|
|
.out_rd (memory_rd),
|
|
.out_wb (memory_wb),
|
|
.out_rs1 (memory_rs1),
|
|
.out_rs2 (memory_rs2),
|
|
.out_branch_dir (memory_branch_dir),
|
|
.out_branch_dest (memory_branch_dest),
|
|
.out_delay (memory_delay),
|
|
.out_PC_next (memory_PC_next),
|
|
.out_valid (memory_valid),
|
|
.out_warp_num (memory_warp_num),
|
|
.out_cache_driver_in_address (out_cache_driver_in_address),
|
|
.out_cache_driver_in_mem_read (out_cache_driver_in_mem_read),
|
|
.out_cache_driver_in_mem_write(out_cache_driver_in_mem_write),
|
|
.out_cache_driver_in_data (out_cache_driver_in_data),
|
|
.out_cache_driver_in_valid (out_cache_driver_in_valid)
|
|
);
|
|
|
|
VX_m_w_reg vx_m_w_reg(
|
|
.clk (clk),
|
|
.in_alu_result (memory_alu_result),
|
|
.in_mem_result (memory_mem_result),
|
|
.in_rd (memory_rd),
|
|
.in_wb (memory_wb),
|
|
.in_rs1 (memory_rs1),
|
|
.in_rs2 (memory_rs2),
|
|
.in_PC_next (memory_PC_next),
|
|
.in_freeze (total_freeze),
|
|
.in_valid (memory_valid),
|
|
.in_warp_num (memory_warp_num),
|
|
|
|
.out_alu_result(m_w_alu_result),
|
|
.out_mem_result(m_w_mem_result),
|
|
.out_rd (m_w_rd),
|
|
.out_wb (m_w_wb),
|
|
.out_rs1 (m_w_rs1),
|
|
.out_rs2 (m_w_rs2),
|
|
.out_PC_next (m_w_PC_next),
|
|
.out_valid (m_w_valid),
|
|
.out_warp_num (m_w_warp_num)
|
|
);
|
|
|
|
|
|
VX_writeback vx_writeback(
|
|
.clk (clk),
|
|
.in_alu_result (m_w_alu_result),
|
|
.in_mem_result (m_w_mem_result),
|
|
.in_rd (m_w_rd),
|
|
.in_wb (m_w_wb),
|
|
.in_PC_next (m_w_PC_next),
|
|
.in_valid (m_w_valid),
|
|
.in_warp_num (m_w_warp_num),
|
|
|
|
.out_write_data(writeback_write_data),
|
|
.out_rd (writeback_rd),
|
|
.out_wb (writeback_wb),
|
|
.out_warp_num (writeback_warp_num)
|
|
);
|
|
|
|
|
|
VX_forwarding vx_forwarding(
|
|
.in_decode_src1 (decode_rs1),
|
|
.in_decode_src2 (decode_rs2),
|
|
.in_decode_csr_address (decode_csr_address),
|
|
.in_decode_warp_num (decode_warp_num),
|
|
|
|
.in_execute_dest (execute_rd),
|
|
.in_execute_wb (execute_wb),
|
|
.in_execute_alu_result (execute_alu_result),
|
|
.in_execute_PC_next (execute_PC_next),
|
|
.in_execute_is_csr (execute_is_csr),
|
|
.in_execute_csr_address (execute_csr_address),
|
|
.in_execute_warp_num (execute_warp_num),
|
|
|
|
.in_memory_dest (memory_rd),
|
|
.in_memory_wb (memory_wb),
|
|
.in_memory_alu_result (memory_alu_result),
|
|
.in_memory_mem_data (memory_mem_result),
|
|
.in_memory_PC_next (memory_PC_next),
|
|
.in_memory_is_csr (e_m_is_csr),
|
|
.in_memory_csr_address (e_m_csr_address),
|
|
.in_memory_csr_result (e_m_csr_result),
|
|
.in_memory_warp_num (memory_warp_num),
|
|
|
|
.in_writeback_dest (m_w_rd),
|
|
.in_writeback_wb (m_w_wb),
|
|
.in_writeback_alu_result(m_w_alu_result),
|
|
.in_writeback_mem_data (m_w_mem_result),
|
|
.in_writeback_PC_next (m_w_PC_next),
|
|
.in_writeback_warp_num (writeback_warp_num),
|
|
|
|
.out_src1_fwd (forwarding_src1_fwd),
|
|
.out_src2_fwd (forwarding_src2_fwd),
|
|
.out_csr_fwd (forwarding_csr_fwd),
|
|
.out_src1_fwd_data (forwarding_src1_fwd_data),
|
|
.out_src2_fwd_data (forwarding_src2_fwd_data),
|
|
.out_csr_fwd_data (forwarding_csr_fwd_data),
|
|
.out_fwd_stall (forwarding_fwd_stall)
|
|
);
|
|
|
|
VX_csr_handler vx_csr_handler(
|
|
.clk (clk),
|
|
.in_decode_csr_address(decode_csr_address),
|
|
.in_mem_csr_address (e_m_csr_address),
|
|
.in_mem_is_csr (e_m_is_csr),
|
|
.in_mem_csr_result (e_m_csr_result),
|
|
.in_wb_valid (m_w_valid[0]),
|
|
|
|
.out_decode_csr_data (csr_decode_csr_data)
|
|
);
|
|
|
|
|
|
|
|
|
|
endmodule // Vortex
|
|
|
|
|
|
|
|
|
|
|