Sim Work miss
This commit is contained in:
felsabbagh3
@@ -6,9 +6,9 @@
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.type _start, @function
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.global _start
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_start:
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li a0, 4 # Num Warps
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li a0, 2 # Num Warps
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csrw 0x20, a0 # Setting the number of available warps
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li a0, 8 # Num Threads
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li a0, 1 # Num Threads
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csrw 0x21, a0 # Setting the number of available threads
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csrw mhartid,zero
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csrw misa,zero
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|
||||
:100150002D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2DCF
|
||||
:100160002D2D2D2D2D2D2D2D2D2D2D2D0A00000069
|
||||
:100170000A0A4D6174726978206D756C7469706CCF
|
||||
:0901800069636174696F6E0A0085
|
||||
:10018C000000008104000081080000810C00008147
|
||||
:10019C001000008114000081180000811C000081F7
|
||||
:1001AC002000008124000081280000812C000081A7
|
||||
:1001BC003000008134000081380000813C00008157
|
||||
:1001CC005000008154000081580000815C000081C7
|
||||
:1001DC006000008164000081680000816C00008177
|
||||
:1001EC007000008174000081780000817C00008127
|
||||
:1001FC0084000081880000818C00008190000081C7
|
||||
:1001FC008000008184000081880000818C000081D7
|
||||
:10020C0094000081980000819C000081A000008176
|
||||
:10021C00A4000081A8000081AC000081B000008126
|
||||
:10022C00B4000081B8000081BC000081C0000081D6
|
||||
:10023C00D0000081D4000081D8000081DC00008156
|
||||
:10023C00C4000081C8000081CC000081D000008186
|
||||
:10024C00E0000081E4000081E8000081EC00008106
|
||||
:10025C00F0000081F4000081F8000081FC000081B6
|
||||
:10026C000001008104010081080100810C01008162
|
||||
:10027C001001008114010081180100811C01008112
|
||||
:040000058000000077
|
||||
:00000001FF
|
||||
|
||||
@@ -6,7 +6,7 @@
|
||||
void vx_before_main()
|
||||
{
|
||||
// unsigned num_available_warps = vx_available_warps();
|
||||
for (int i = 0; i < 8; i++)
|
||||
for (int i = 0; i < 32; i++)
|
||||
{
|
||||
queue_initialize(q + i);
|
||||
}
|
||||
@@ -15,9 +15,20 @@ void vx_before_main()
|
||||
void vx_reschedule_warps()
|
||||
{
|
||||
|
||||
|
||||
register unsigned curr_warp asm("s10");
|
||||
// vx_printf("Reschedule: ", curr_warp);
|
||||
vx_printf("Reschedule: ", curr_warp);
|
||||
asm __volatile__("nop");
|
||||
asm __volatile__("nop");
|
||||
asm __volatile__("nop");
|
||||
asm __volatile__("nop");
|
||||
asm __volatile__("nop");
|
||||
asm __volatile__("nop");
|
||||
asm __volatile__("nop");
|
||||
asm __volatile__("nop");
|
||||
asm __volatile__("nop");
|
||||
asm __volatile__("nop");
|
||||
asm __volatile__("nop");
|
||||
asm __volatile__("nop");
|
||||
|
||||
if (queue_isEmpty(q+curr_warp))
|
||||
{
|
||||
@@ -38,7 +49,7 @@ void vx_reschedule_warps()
|
||||
asm __volatile__("mv sp,%0"::"r" (j.base_sp):);
|
||||
vx_createThreads(j.n_threads, j.wid, j.func_ptr, j.args, j.assigned_warp);
|
||||
|
||||
ECALL;
|
||||
ECALL; // should never reach this
|
||||
|
||||
}
|
||||
|
||||
@@ -133,6 +144,7 @@ void vx_wait_for_warps(unsigned num_wait)
|
||||
num += 1;
|
||||
}
|
||||
}
|
||||
// vx_printf("Found: ", num);
|
||||
}
|
||||
|
||||
// vx_printf("num found: ", num);
|
||||
|
||||
@@ -29,11 +29,11 @@
|
||||
#define __end_if AFTER:\
|
||||
JOIN;
|
||||
|
||||
static int done[] = {0, 0, 0, 0, 0, 0, 0};
|
||||
static int done[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
|
||||
|
||||
static int main_sp[1];
|
||||
|
||||
unsigned context[32];
|
||||
unsigned context[64];
|
||||
void vx_save_context(void);
|
||||
void vx_load_context(void);
|
||||
|
||||
|
||||
@@ -6,9 +6,9 @@
|
||||
.type _start, @function
|
||||
.global _start
|
||||
_start:
|
||||
li a0, 2 # Num Warps
|
||||
li a0, 8 # Num Warps
|
||||
csrw 0x20, a0 # Setting the number of available warps
|
||||
li a0, 2 # Num Threads
|
||||
li a0, 4 # Num Threads
|
||||
csrw 0x21, a0 # Setting the number of available threads
|
||||
csrw mhartid,zero
|
||||
csrw misa,zero
|
||||
@@ -46,7 +46,21 @@ loop_done:
|
||||
li a0,0 # setting tid = 0 for main thread
|
||||
mv t6,a2 # setting func_addr
|
||||
mv s11,t2 # setting num_threads to spawn
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
.word 0x1bfe0eb
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
la a0, vx_reschedule_warps
|
||||
.word 0x5406b
|
||||
|
||||
|
||||
@@ -5,8 +5,8 @@
|
||||
|
||||
|
||||
|
||||
#define SIZE 50
|
||||
#define WARPS 7
|
||||
#define SIZE 100
|
||||
#define WARPS 8
|
||||
|
||||
|
||||
typedef struct Job_t
|
||||
@@ -31,7 +31,7 @@ typedef struct Queue_t
|
||||
|
||||
} Queue;
|
||||
|
||||
Queue q[8];
|
||||
Queue q[64];
|
||||
|
||||
void queue_initialize(Queue *);
|
||||
|
||||
|
||||
@@ -58,6 +58,12 @@ ec:
|
||||
queue_dequeue:
|
||||
mv t0, a0 # loading base address of q
|
||||
lw t1, 8 (t0) # t1 = num_j
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
addi t1, t1, -1 # --t1
|
||||
sw t1, 8 (t0) # num_j = t1
|
||||
addi t1, t0, 20 # t1 = jobs_addr
|
||||
|
||||
@@ -3,7 +3,9 @@
|
||||
|
||||
module VX_context (
|
||||
input wire clk,
|
||||
/* verilator lint_off UNUSED */
|
||||
input wire in_warp,
|
||||
/* verilator lint_on UNUSED */
|
||||
input wire in_wb_warp,
|
||||
input wire in_valid[`NT_M1:0],
|
||||
input wire in_write_register,
|
||||
|
||||
@@ -3,7 +3,9 @@
|
||||
|
||||
module VX_context_slave (
|
||||
input wire clk,
|
||||
/* verilator lint_off UNUSED */
|
||||
input wire in_warp,
|
||||
/* verilator lint_on UNUSED */
|
||||
input wire in_wb_warp,
|
||||
input wire in_valid[`NT_M1:0],
|
||||
input wire in_write_register,
|
||||
|
||||
228
rtl/VX_decode.v
228
rtl/VX_decode.v
@@ -19,6 +19,9 @@ module VX_decode(
|
||||
input wire[31:0] in_src1_fwd_data[`NT_M1:0],
|
||||
input wire in_src2_fwd,
|
||||
input wire[31:0] in_src2_fwd_data[`NT_M1:0],
|
||||
/* verilator lint_off UNUSED */
|
||||
input wire[`NW_M1:0] in_which_wspawn,
|
||||
/* verilator lint_on UNUSED */
|
||||
|
||||
input wire[`NW_M1:0] in_warp_num,
|
||||
|
||||
@@ -111,78 +114,181 @@ module VX_decode(
|
||||
reg[4:0] alu_op;
|
||||
reg[4:0] mul_alu;
|
||||
|
||||
/* verilator lint_off UNUSED */
|
||||
wire[31:0] w0_t0_registers[31:0];
|
||||
/* verilator lint_on UNUSED */
|
||||
|
||||
|
||||
wire context_zero_valid = (in_wb_warp_num == 0);
|
||||
wire[31:0] zero_a_reg_data[`NT_M1:0];
|
||||
wire[31:0] zero_b_reg_data[`NT_M1:0];
|
||||
reg zero_clone_stall;
|
||||
|
||||
// always @(*) begin
|
||||
// $display("DECODE WARP: %h", in_warp_num);
|
||||
// end
|
||||
|
||||
wire curr_warp_zero = in_warp_num == 0;
|
||||
wire curr_warp_one = in_warp_num == 1;
|
||||
|
||||
// always @(*) begin
|
||||
// $display("DECODE WARP: %h PC: %h",in_warp_num, in_curr_PC);
|
||||
// end
|
||||
|
||||
VX_context VX_Context_zero(
|
||||
.clk (clk),
|
||||
.in_warp (curr_warp_zero),
|
||||
.in_wb_warp (context_zero_valid),
|
||||
.in_valid (in_wb_valid),
|
||||
.in_rd (in_rd),
|
||||
.in_src1 (out_rs1),
|
||||
.in_src2 (out_rs2),
|
||||
.in_curr_PC (in_curr_PC),
|
||||
.in_is_clone (is_clone),
|
||||
.in_is_jal (is_jal),
|
||||
.in_src1_fwd (in_src1_fwd),
|
||||
.in_src1_fwd_data (in_src1_fwd_data),
|
||||
.in_src2_fwd (in_src2_fwd),
|
||||
.in_src2_fwd_data (in_src2_fwd_data),
|
||||
.in_write_register(write_register),
|
||||
.in_write_data (in_write_data),
|
||||
.out_a_reg_data (zero_a_reg_data),
|
||||
.out_b_reg_data (zero_b_reg_data),
|
||||
.out_clone_stall (zero_clone_stall),
|
||||
.w0_t0_registers (w0_t0_registers)
|
||||
);
|
||||
`ifdef ONLY
|
||||
|
||||
wire context_one_valid = (in_wb_warp_num == 1);
|
||||
wire[31:0] one_a_reg_data[`NT_M1:0];
|
||||
wire[31:0] one_b_reg_data[`NT_M1:0];
|
||||
reg one_clone_stall;
|
||||
VX_context_slave VX_Context_one(
|
||||
.clk (clk),
|
||||
.in_warp (curr_warp_one),
|
||||
.in_wb_warp (context_one_valid),
|
||||
.in_valid (in_wb_valid),
|
||||
.in_rd (in_rd),
|
||||
.in_src1 (out_rs1),
|
||||
.in_src2 (out_rs2),
|
||||
.in_curr_PC (in_curr_PC),
|
||||
.in_is_clone (is_clone),
|
||||
.in_is_jal (is_jal),
|
||||
.in_src1_fwd (in_src1_fwd),
|
||||
.in_src1_fwd_data (in_src1_fwd_data),
|
||||
.in_src2_fwd (in_src2_fwd),
|
||||
.in_src2_fwd_data (in_src2_fwd_data),
|
||||
.in_write_register(write_register),
|
||||
.in_write_data (in_write_data),
|
||||
.in_wspawn_regs (w0_t0_registers),
|
||||
.in_wspawn (is_wspawn),
|
||||
.out_a_reg_data (one_a_reg_data),
|
||||
.out_b_reg_data (one_b_reg_data),
|
||||
.out_clone_stall (one_clone_stall)
|
||||
);
|
||||
wire[31:0] glob_a_reg_data[`NT_M1:0];
|
||||
wire[31:0] glob_b_reg_data[`NT_M1:0];
|
||||
reg glob_clone_stall;
|
||||
|
||||
assign out_a_reg_data = curr_warp_zero ? zero_a_reg_data : one_a_reg_data;
|
||||
assign out_b_reg_data = curr_warp_zero ? zero_b_reg_data : one_b_reg_data;
|
||||
assign out_clone_stall = zero_clone_stall || one_clone_stall;
|
||||
wire curr_warp_zero = in_warp_num == 0;
|
||||
wire context_zero_valid = (in_wb_warp_num == 0);
|
||||
wire real_zero_isclone = is_clone && (in_warp_num == 0);
|
||||
VX_context VX_Context_zero(
|
||||
.clk (clk),
|
||||
.in_warp (curr_warp_zero),
|
||||
.in_wb_warp (context_zero_valid),
|
||||
.in_valid (in_wb_valid),
|
||||
.in_rd (in_rd),
|
||||
.in_src1 (out_rs1),
|
||||
.in_src2 (out_rs2),
|
||||
.in_curr_PC (in_curr_PC),
|
||||
.in_is_clone (real_zero_isclone),
|
||||
.in_is_jal (is_jal),
|
||||
.in_src1_fwd (in_src1_fwd),
|
||||
.in_src1_fwd_data (in_src1_fwd_data),
|
||||
.in_src2_fwd (in_src2_fwd),
|
||||
.in_src2_fwd_data (in_src2_fwd_data),
|
||||
.in_write_register(write_register),
|
||||
.in_write_data (in_write_data),
|
||||
.out_a_reg_data (glob_a_reg_data),
|
||||
.out_b_reg_data (glob_b_reg_data),
|
||||
.out_clone_stall (glob_clone_stall),
|
||||
.w0_t0_registers (w0_t0_registers)
|
||||
);
|
||||
|
||||
|
||||
assign out_a_reg_data = glob_a_reg_data;
|
||||
assign out_b_reg_data = glob_b_reg_data;
|
||||
assign out_clone_stall = glob_clone_stall;
|
||||
|
||||
`else
|
||||
|
||||
wire[31:0] glob_a_reg_data[`NW-1:0][`NT_M1:0];
|
||||
wire[31:0] glob_b_reg_data[`NW-1:0][`NT_M1:0];
|
||||
reg glob_clone_stall[`NW-1:0];
|
||||
|
||||
wire curr_warp_zero = in_warp_num == 0;
|
||||
wire context_zero_valid = (in_wb_warp_num == 0);
|
||||
wire real_zero_isclone = is_clone && (in_warp_num == 0);
|
||||
VX_context VX_Context_zero(
|
||||
.clk (clk),
|
||||
.in_warp (curr_warp_zero),
|
||||
.in_wb_warp (context_zero_valid),
|
||||
.in_valid (in_wb_valid),
|
||||
.in_rd (in_rd),
|
||||
.in_src1 (out_rs1),
|
||||
.in_src2 (out_rs2),
|
||||
.in_curr_PC (in_curr_PC),
|
||||
.in_is_clone (real_zero_isclone),
|
||||
.in_is_jal (is_jal),
|
||||
.in_src1_fwd (in_src1_fwd),
|
||||
.in_src1_fwd_data (in_src1_fwd_data),
|
||||
.in_src2_fwd (in_src2_fwd),
|
||||
.in_src2_fwd_data (in_src2_fwd_data),
|
||||
.in_write_register(write_register),
|
||||
.in_write_data (in_write_data),
|
||||
.out_a_reg_data (glob_a_reg_data[0]),
|
||||
.out_b_reg_data (glob_b_reg_data[0]),
|
||||
.out_clone_stall (glob_clone_stall[0]),
|
||||
.w0_t0_registers (w0_t0_registers)
|
||||
);
|
||||
|
||||
genvar r;
|
||||
generate
|
||||
for (r = 1; r < `NW; r = r + 1) begin
|
||||
wire context_glob_valid = (in_wb_warp_num == r);
|
||||
wire curr_warp_glob = in_warp_num == r;
|
||||
wire real_wspawn = is_wspawn && (in_which_wspawn == r);
|
||||
wire real_isclone = is_clone && (in_warp_num == r);
|
||||
VX_context_slave VX_Context_one(
|
||||
.clk (clk),
|
||||
.in_warp (curr_warp_glob),
|
||||
.in_wb_warp (context_glob_valid),
|
||||
.in_valid (in_wb_valid),
|
||||
.in_rd (in_rd),
|
||||
.in_src1 (out_rs1),
|
||||
.in_src2 (out_rs2),
|
||||
.in_curr_PC (in_curr_PC),
|
||||
.in_is_clone (real_isclone),
|
||||
.in_is_jal (is_jal),
|
||||
.in_src1_fwd (in_src1_fwd),
|
||||
.in_src1_fwd_data (in_src1_fwd_data),
|
||||
.in_src2_fwd (in_src2_fwd),
|
||||
.in_src2_fwd_data (in_src2_fwd_data),
|
||||
.in_write_register(write_register),
|
||||
.in_write_data (in_write_data),
|
||||
.in_wspawn_regs (w0_t0_registers),
|
||||
.in_wspawn (real_wspawn),
|
||||
.out_a_reg_data (glob_a_reg_data[r]),
|
||||
.out_b_reg_data (glob_b_reg_data[r]),
|
||||
.out_clone_stall (glob_clone_stall[r])
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// always @(posedge clk)
|
||||
// if(write_register && (in_wb_warp == 3) && (in_wb_valid[0]) && (in_rd == 31)) begin
|
||||
|
||||
// $display("Warp 3 writing ",);
|
||||
// end
|
||||
// end
|
||||
|
||||
reg[31:0] temp_out_a_reg_data[`NT_M1:0];
|
||||
reg[31:0] temp_out_b_reg_data[`NT_M1:0];
|
||||
/* verilator lint_off UNOPTFLAT */
|
||||
reg temp_out_clone_stall;
|
||||
/* verilator lint_on UNOPTFLAT */
|
||||
|
||||
always @(*) begin
|
||||
|
||||
if (`NW == 1) begin
|
||||
temp_out_a_reg_data = glob_a_reg_data;
|
||||
temp_out_b_reg_data = glob_b_reg_data;
|
||||
end else begin
|
||||
integer g;
|
||||
// temp_out_clone_stall = 0;
|
||||
for (g = 0; g < `NW; g = g + 1)
|
||||
begin
|
||||
if (in_warp_num == g[`NW_M1:0]) begin
|
||||
temp_out_a_reg_data = glob_a_reg_data[g];
|
||||
temp_out_b_reg_data = glob_b_reg_data[g];
|
||||
end
|
||||
|
||||
// temp_out_clone_stall = temp_out_clone_stall || glob_clone_stall[g];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign out_a_reg_data = temp_out_a_reg_data;
|
||||
assign out_b_reg_data = temp_out_b_reg_data;
|
||||
// assign out_clone_stall = temp_out_clone_stall;
|
||||
|
||||
// assign out_a_reg_data = curr_warp_zero ? glob_a_reg_data[0] : glob_a_reg_data[1];
|
||||
// assign out_b_reg_data = curr_warp_zero ? glob_b_reg_data[0] : glob_b_reg_data[1];
|
||||
|
||||
genvar y;
|
||||
generate
|
||||
always @(*) begin
|
||||
temp_out_clone_stall = glob_clone_stall[0];
|
||||
for (y = 1; y < `NW; y = y+1) begin
|
||||
temp_out_clone_stall = temp_out_clone_stall || glob_clone_stall[y];
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign out_clone_stall = temp_out_clone_stall;
|
||||
|
||||
|
||||
`endif
|
||||
|
||||
|
||||
// assign out_clone_stall = glob_clone_stall[0] || glob_clone_stall[1] ||
|
||||
// glob_clone_stall[2] || glob_clone_stall[3];
|
||||
|
||||
// always @(*) begin
|
||||
// if (context_one_valid) begin
|
||||
@@ -234,7 +340,7 @@ module VX_decode(
|
||||
assign out_wspawn_pc = out_a_reg_data[0];
|
||||
|
||||
// always @(*) begin
|
||||
// if (is_jalrs) begin
|
||||
// if (is_jalrs && in_warp_num == 2) begin
|
||||
// $display("JALRS WOHOOO: rs2 - %h", out_b_reg_data[0]);
|
||||
// end
|
||||
// end
|
||||
@@ -274,9 +380,6 @@ module VX_decode(
|
||||
|
||||
|
||||
|
||||
// ch_print("DECODE: PC: {0}, INSTRUCTION: {1}", in_curr_PC, in_instruction);
|
||||
|
||||
|
||||
|
||||
// assign out_reg_data[0] = ( (is_jal == 1'b1) ? in_curr_PC : ((in_src1_fwd == 1'b1) ? in_src1_fwd_data[0] : rd1_register[0]));
|
||||
// assign out_reg_data[1] = (in_src2_fwd == 1'b1) ? in_src2_fwd_data[0] : rd2_register[0];
|
||||
@@ -361,6 +464,7 @@ module VX_decode(
|
||||
begin
|
||||
if (is_jalrs || is_jmprt)
|
||||
begin
|
||||
// $display("OUT JAL DEST: %h", out_a_reg_data[0]);
|
||||
out_jal = 1'b1 && in_valid[0];
|
||||
out_jal_offset = 32'h0;
|
||||
end
|
||||
|
||||
@@ -1,7 +1,10 @@
|
||||
|
||||
|
||||
#define NT 2
|
||||
#define NT_M1 1
|
||||
#define NT 4
|
||||
#define NT_M1 (NT-1)
|
||||
|
||||
#define NW 8
|
||||
|
||||
|
||||
#define R_INST 51
|
||||
#define L_INST 3
|
||||
|
||||
@@ -1,8 +1,11 @@
|
||||
|
||||
`define NT 2
|
||||
`define NT_M1 1
|
||||
|
||||
`define NW_M1 1
|
||||
`define NT 4
|
||||
`define NT_M1 (`NT-1)
|
||||
|
||||
`define NW_M1 3
|
||||
`define NW 8
|
||||
// `define ONLY
|
||||
|
||||
|
||||
`define R_INST 7'd51
|
||||
|
||||
202
rtl/VX_fetch.v
202
rtl/VX_fetch.v
@@ -29,7 +29,8 @@ module VX_fetch (
|
||||
output wire[`NW_M1:0] out_warp_num,
|
||||
output wire[31:0] out_curr_PC,
|
||||
output wire out_valid[`NT_M1:0],
|
||||
output wire out_ebreak
|
||||
output wire out_ebreak,
|
||||
output wire[`NW_M1:0] out_which_wspawn
|
||||
);
|
||||
|
||||
reg stall;
|
||||
@@ -37,108 +38,161 @@ module VX_fetch (
|
||||
|
||||
reg[`NW_M1:0] warp_num;
|
||||
reg[`NW_M1:0] warp_state;
|
||||
reg[`NW_M1:0] warp_count;
|
||||
|
||||
reg[31:0] num_ecalls;
|
||||
|
||||
initial begin
|
||||
warp_num = 0;
|
||||
warp_state = 0;
|
||||
num_ecalls = 0;
|
||||
warp_count = 1;
|
||||
end
|
||||
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (in_ebreak) begin
|
||||
num_ecalls <= num_ecalls + 1;
|
||||
$display("--------> New num_ecalls = %h", num_ecalls+1);
|
||||
end
|
||||
end
|
||||
|
||||
wire add_warp = in_wspawn && !in_ebreak && !in_clone_stall;
|
||||
wire remove_warp = in_ebreak && !in_wspawn && !in_clone_stall;
|
||||
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset || (warp_num == warp_state) || remove_warp || add_warp) begin
|
||||
if (reset || (warp_num >= warp_state) || remove_warp || add_warp) begin
|
||||
warp_num <= 0;
|
||||
`ifndef ONLY
|
||||
end else if (!warp_glob_valid[warp_num+1]) begin
|
||||
$display("Skipping one");
|
||||
warp_num <= warp_num + 2;
|
||||
`endif
|
||||
end else begin
|
||||
warp_num <= warp_num + 1;
|
||||
end
|
||||
|
||||
if (add_warp) begin
|
||||
// $display("Adding a new warp %h", warp_state);
|
||||
warp_state <= warp_state + 1;
|
||||
end else if (remove_warp) begin
|
||||
// $display("Removing a warp %h", warp_state);
|
||||
warp_state <= warp_state - 1;
|
||||
warp_count <= warp_count + 1;
|
||||
$display("Adding a new warp %h", warp_state+1);
|
||||
end else if (remove_warp) begin // No removing, just invalidating
|
||||
warp_count <= warp_count - 1;
|
||||
$display("Removing a warp %h %h", in_decode_warp_num, warp_count);
|
||||
if (warp_count == 2) begin
|
||||
$display("&&&&&&&&&&&&& STATE 0");
|
||||
warp_state <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign out_ebreak = (warp_state == 0) && in_ebreak;
|
||||
assign out_ebreak = (in_decode_warp_num == 0) && in_ebreak;
|
||||
|
||||
|
||||
assign stall = in_clone_stall || in_branch_stall || in_fwd_stall || in_branch_stall_exe || in_interrupt || in_freeze || in_debug;
|
||||
|
||||
assign out_which_wspawn = (warp_state+1);
|
||||
|
||||
`ifdef ONLY
|
||||
|
||||
wire warp_zero_change_mask = in_change_mask && (in_decode_warp_num == 0);
|
||||
wire warp_zero_jal = in_jal && (in_memory_warp_num == 0);
|
||||
wire warp_zero_branch = in_branch_dir && (in_memory_warp_num == 0);
|
||||
wire warp_zero_stall = stall || (warp_num != 0);
|
||||
wire warp_zero_wspawn = (0 == 0) ? 0 : (in_wspawn && ((warp_state+1) == 0));
|
||||
wire[31:0] warp_zero_wspawn_pc = in_wspawn_pc;
|
||||
wire warp_zero_remove = remove_warp && (in_decode_warp_num == 0);
|
||||
|
||||
always @(*) begin : proc_
|
||||
if (warp_zero_remove) $display("4Removing warp: %h", 0);
|
||||
end
|
||||
|
||||
VX_warp VX_Warp(
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.stall (warp_zero_stall),
|
||||
.remove (warp_zero_remove),
|
||||
.in_thread_mask(in_thread_mask),
|
||||
.in_change_mask(warp_zero_change_mask),
|
||||
.in_jal (warp_zero_jal),
|
||||
.in_jal_dest (in_jal_dest),
|
||||
.in_branch_dir (warp_zero_branch),
|
||||
.in_branch_dest(in_branch_dest),
|
||||
.in_wspawn (warp_zero_wspawn),
|
||||
.in_wspawn_pc (warp_zero_wspawn_pc),
|
||||
.out_PC (out_PC),
|
||||
.out_valid (out_valid)
|
||||
);
|
||||
|
||||
`else
|
||||
|
||||
wire[31:0] warp_glob_pc[`NW-1:0];
|
||||
wire warp_glob_valid[`NW-1:0][`NT_M1:0];
|
||||
genvar cur_warp;
|
||||
generate
|
||||
for (cur_warp = 0; cur_warp < `NW; cur_warp = cur_warp + 1)
|
||||
begin
|
||||
wire warp_zero_change_mask = in_change_mask && (in_decode_warp_num == cur_warp);
|
||||
wire warp_zero_jal = in_jal && (in_memory_warp_num == cur_warp);
|
||||
wire warp_zero_branch = in_branch_dir && (in_memory_warp_num == cur_warp);
|
||||
wire warp_zero_stall = stall || (warp_num != cur_warp);
|
||||
wire warp_zero_wspawn = (cur_warp == 0) ? 0 : (in_wspawn && ((warp_state+1) == cur_warp));
|
||||
wire[31:0] warp_zero_wspawn_pc = in_wspawn_pc;
|
||||
wire warp_zero_remove = remove_warp && (in_decode_warp_num == cur_warp);
|
||||
|
||||
always @(*) begin : proc_
|
||||
if (warp_zero_remove) $display("4Removing warp: %h", cur_warp);
|
||||
end
|
||||
|
||||
VX_warp VX_Warp(
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.stall (warp_zero_stall),
|
||||
.remove (warp_zero_remove),
|
||||
.in_thread_mask(in_thread_mask),
|
||||
.in_change_mask(warp_zero_change_mask),
|
||||
.in_jal (warp_zero_jal),
|
||||
.in_jal_dest (in_jal_dest),
|
||||
.in_branch_dir (warp_zero_branch),
|
||||
.in_branch_dest(in_branch_dest),
|
||||
.in_wspawn (warp_zero_wspawn),
|
||||
.in_wspawn_pc (warp_zero_wspawn_pc),
|
||||
.out_PC (warp_glob_pc[cur_warp]),
|
||||
.out_valid (warp_glob_valid[cur_warp])
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
wire warp_zero_change_mask = in_change_mask && (in_decode_warp_num == 0);
|
||||
wire warp_zero_jal = in_jal && (in_memory_warp_num == 0);
|
||||
wire warp_zero_branch = in_branch_dir && (in_memory_warp_num == 0);
|
||||
wire warp_zero_stall = stall || (warp_num == 1);
|
||||
wire warp_zero_wspawn = 0;
|
||||
wire[31:0] warp_zero_wspawn_pc = 32'h0;
|
||||
reg[31:0] out_PC_var;
|
||||
reg out_valid_var[`NT_M1:0];
|
||||
|
||||
wire[31:0] warp_zero_pc;
|
||||
wire warp_zero_valid[`NT_M1:0];
|
||||
VX_warp VX_Warp_zero(
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.stall (warp_zero_stall),
|
||||
.in_thread_mask(in_thread_mask),
|
||||
.in_change_mask(warp_zero_change_mask),
|
||||
.in_jal (warp_zero_jal),
|
||||
.in_jal_dest (in_jal_dest),
|
||||
.in_branch_dir (warp_zero_branch),
|
||||
.in_branch_dest(in_branch_dest),
|
||||
.in_wspawn (warp_zero_wspawn),
|
||||
.in_wspawn_pc (warp_zero_wspawn_pc),
|
||||
.out_PC (warp_zero_pc),
|
||||
.out_valid (warp_zero_valid)
|
||||
);
|
||||
always @(*) begin : help
|
||||
integer g;
|
||||
integer h;
|
||||
for (g = 0; g < `NW; g = g + 1)
|
||||
begin
|
||||
if (warp_num == g[`NW_M1:0])
|
||||
begin
|
||||
out_PC_var = warp_glob_pc[g][31:0];
|
||||
for (h = 0; h < `NT; h = h + 1) out_valid_var[h] = warp_glob_valid[g][h];
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
assign out_PC = out_PC_var;
|
||||
assign out_valid = out_valid_var;
|
||||
|
||||
always @(*) begin
|
||||
if (out_valid[0]) begin
|
||||
$display("[%d] %h #%b#",out_warp_num, out_PC, out_valid);
|
||||
end
|
||||
end
|
||||
|
||||
`endif
|
||||
|
||||
|
||||
wire warp_one_change_mask = in_change_mask && (in_decode_warp_num == 1);
|
||||
wire warp_one_jal = in_jal && (in_memory_warp_num == 1);
|
||||
wire warp_one_branch = in_branch_dir && (in_memory_warp_num == 1);
|
||||
wire warp_one_stall = stall || (warp_num == 0);
|
||||
wire[31:0] warp_one_pc;
|
||||
wire warp_one_valid[`NT_M1:0];
|
||||
VX_warp VX_Warp_one(
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.stall (warp_one_stall),
|
||||
.in_thread_mask(in_thread_mask),
|
||||
.in_change_mask(warp_one_change_mask),
|
||||
.in_jal (warp_one_jal),
|
||||
.in_jal_dest (in_jal_dest),
|
||||
.in_branch_dir (warp_one_branch),
|
||||
.in_branch_dest(in_branch_dest),
|
||||
.in_wspawn (in_wspawn),
|
||||
.in_wspawn_pc (in_wspawn_pc),
|
||||
.out_PC (warp_one_pc),
|
||||
.out_valid (warp_one_valid)
|
||||
);
|
||||
|
||||
// always @(*) begin
|
||||
// if (in_wspawn) begin
|
||||
// $display("Spawning a warp @ %h",in_wspawn_pc);
|
||||
// end
|
||||
// end
|
||||
|
||||
// always @(posedge clk) begin
|
||||
// $display("curr warp: %h Threads:%d%d PC: %h", warp_num, out_valid[0],out_valid[1], out_PC);
|
||||
// end
|
||||
|
||||
// always @(*) begin
|
||||
// if (warp_num == 1) begin
|
||||
// $display("Going to PC: %h", warp_one_pc);
|
||||
// end
|
||||
// end
|
||||
|
||||
assign out_PC = (warp_num == 0) ? warp_zero_pc : warp_one_pc;
|
||||
assign out_valid = (warp_num == 0) ? warp_zero_valid : warp_one_valid;
|
||||
|
||||
// always @(*) begin
|
||||
// $display("FETCH PC: %h (%h, %h, %h)",delete, delete, in_jal_dest, in_branch_dest);
|
||||
// end
|
||||
|
||||
|
||||
assign out_curr_PC = out_PC;
|
||||
|
||||
@@ -5,6 +5,7 @@ module VX_warp (
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
input wire stall,
|
||||
input wire remove,
|
||||
input wire in_thread_mask[`NT_M1:0],
|
||||
input wire in_change_mask,
|
||||
input wire in_jal,
|
||||
@@ -23,18 +24,24 @@ module VX_warp (
|
||||
var[31:0] use_PC;
|
||||
reg valid[`NT_M1:0];
|
||||
|
||||
reg valid_zero[`NT_M1:0];
|
||||
|
||||
integer ini_cur_th = 0;
|
||||
initial begin
|
||||
real_PC = 0;
|
||||
for (ini_cur_th = 1; ini_cur_th < `NT; ini_cur_th=ini_cur_th+1)
|
||||
for (ini_cur_th = 1; ini_cur_th < `NT; ini_cur_th=ini_cur_th+1) begin
|
||||
valid[ini_cur_th] = 0; // Thread 1 active
|
||||
valid[0] = 1;
|
||||
valid_zero[ini_cur_th] = 0;
|
||||
end
|
||||
valid[0] = 1;
|
||||
valid_zero[0] = 0;
|
||||
end
|
||||
|
||||
|
||||
always @(*) begin
|
||||
if (in_change_mask) begin
|
||||
if (remove) begin
|
||||
assign valid = valid_zero;
|
||||
end else if (in_change_mask) begin
|
||||
assign valid = in_thread_mask;
|
||||
end
|
||||
end
|
||||
@@ -50,6 +57,7 @@ module VX_warp (
|
||||
always @(*) begin
|
||||
if (in_jal == 1'b1) begin
|
||||
temp_PC = in_jal_dest;
|
||||
// $display("LINKING TO %h", temp_PC);
|
||||
end else if (in_branch_dir == 1'b1) begin
|
||||
temp_PC = in_branch_dest;
|
||||
end else begin
|
||||
|
||||
@@ -32,6 +32,7 @@ wire[31:0] fetch_curr_PC;
|
||||
wire fetch_valid[`NT_M1:0];
|
||||
wire[`NW_M1:0] fetch_warp_num;
|
||||
wire fetch_ebreak;
|
||||
wire[`NW_M1:0] fetch_which_warp;
|
||||
|
||||
// From f_d_register
|
||||
wire[31:0] f_d_instruction;
|
||||
@@ -228,7 +229,8 @@ VX_fetch vx_fetch(
|
||||
.out_curr_PC (fetch_curr_PC),
|
||||
.out_warp_num (fetch_warp_num),
|
||||
.out_valid (fetch_valid),
|
||||
.out_ebreak (fetch_ebreak)
|
||||
.out_ebreak (fetch_ebreak),
|
||||
.out_which_wspawn (fetch_which_warp)
|
||||
);
|
||||
|
||||
|
||||
@@ -264,6 +266,7 @@ VX_decode vx_decode(
|
||||
.in_src2_fwd (forwarding_src2_fwd),
|
||||
.in_src2_fwd_data(forwarding_src2_fwd_data),
|
||||
.in_warp_num (f_d_warp_num),
|
||||
.in_which_wspawn (fetch_which_warp),
|
||||
|
||||
.out_csr_address (decode_csr_address),
|
||||
.out_is_csr (decode_is_csr),
|
||||
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
@@ -1,361 +0,0 @@
|
||||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Primary design header
|
||||
//
|
||||
// This header should be included by all source files instantiating the design.
|
||||
// The class here is then constructed to instantiate the design.
|
||||
// See the Verilator manual for examples.
|
||||
|
||||
#ifndef _VVortex_H_
|
||||
#define _VVortex_H_
|
||||
|
||||
#include "verilated.h"
|
||||
|
||||
class VVortex__Syms;
|
||||
|
||||
//----------
|
||||
|
||||
VL_MODULE(VVortex) {
|
||||
public:
|
||||
|
||||
// PORTS
|
||||
// The application code writes and reads these signals to
|
||||
// propagate new values into/out from the Verilated model.
|
||||
// Begin mtask footprint all:
|
||||
VL_IN8(clk,0,0);
|
||||
VL_IN8(reset,0,0);
|
||||
VL_OUT8(out_cache_driver_in_mem_read,2,0);
|
||||
VL_OUT8(out_cache_driver_in_mem_write,2,0);
|
||||
VL_OUT8(out_ebreak,0,0);
|
||||
VL_IN(fe_instruction,31,0);
|
||||
VL_OUT(curr_PC,31,0);
|
||||
VL_IN(in_cache_driver_out_data[2],31,0);
|
||||
VL_OUT(out_cache_driver_in_address[2],31,0);
|
||||
VL_OUT8(out_cache_driver_in_valid[2],0,0);
|
||||
VL_OUT(out_cache_driver_in_data[2],31,0);
|
||||
|
||||
// LOCAL SIGNALS
|
||||
// Internals; generally not touched by application code
|
||||
// Anonymous structures to workaround compiler member-count bugs
|
||||
struct {
|
||||
// Begin mtask footprint all:
|
||||
VL_SIG8(Vortex__DOT__decode_branch_stall,0,0);
|
||||
VL_SIG8(Vortex__DOT__decode_branch_type,2,0);
|
||||
VL_SIG8(Vortex__DOT__decode_jal,0,0);
|
||||
VL_SIG8(Vortex__DOT__decode_clone_stall,0,0);
|
||||
VL_SIG8(Vortex__DOT__decode_change_mask,0,0);
|
||||
VL_SIG8(Vortex__DOT__execute_branch_stall,0,0);
|
||||
VL_SIG8(Vortex__DOT__memory_branch_dir,0,0);
|
||||
VL_SIG8(Vortex__DOT__forwarding_fwd_stall,0,0);
|
||||
VL_SIG8(Vortex__DOT__forwarding_src1_fwd,0,0);
|
||||
VL_SIG8(Vortex__DOT__forwarding_src2_fwd,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__stall,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_num,1,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_state,1,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__add_warp,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__remove_warp,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_zero_change_mask,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_zero_stall,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_one_change_mask,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_one_stall,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__warp_num,1,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_itype,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_csr,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_clone,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_jalrs,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_jmprt,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_wspawn,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__jal_sys_jal,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__mul_alu,4,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_ebreak,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__temp_final_alu,4,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall,5,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_state_stall,5,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__wspawn_state_stall,5,0);
|
||||
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__rd,4,0);
|
||||
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__alu_op,4,0);
|
||||
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__wb,1,0);
|
||||
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__rs2_src,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__mem_read,2,0);
|
||||
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__mem_write,2,0);
|
||||
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__branch_type,2,0);
|
||||
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__is_csr,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__jal,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__warp_num,1,0);
|
||||
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__stalling,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__rd,4,0);
|
||||
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__wb,1,0);
|
||||
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__mem_read,2,0);
|
||||
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__mem_write,2,0);
|
||||
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__is_csr,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__branch_type,2,0);
|
||||
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__jal,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__warp_num,1,0);
|
||||
VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__rd,4,0);
|
||||
VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__wb,1,0);
|
||||
VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__warp_num,1,0);
|
||||
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd,0,0);
|
||||
VL_SIG16(Vortex__DOT__decode_csr_address,11,0);
|
||||
VL_SIG16(Vortex__DOT__vx_decode__DOT__alu_tempp,11,0);
|
||||
VL_SIG16(Vortex__DOT__vx_d_e_reg__DOT__csr_address,11,0);
|
||||
};
|
||||
struct {
|
||||
VL_SIG16(Vortex__DOT__vx_e_m_reg__DOT__csr_address,11,0);
|
||||
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__decode_csr_address,11,0);
|
||||
VL_SIG(Vortex__DOT__decode_itype_immed,31,0);
|
||||
VL_SIG(Vortex__DOT__decode_jal_offset,31,0);
|
||||
VL_SIG(Vortex__DOT__memory_branch_dest,31,0);
|
||||
VL_SIG(Vortex__DOT__csr_decode_csr_data,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__out_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__VX_Warp_zero__DOT__real_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__VX_Warp_zero__DOT__temp_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__VX_Warp_one__DOT__real_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__VX_Warp_one__DOT__temp_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_f_d_reg__DOT__instruction,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_f_d_reg__DOT__curr_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__PC_next_out,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__itype_immed,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__upper_immed,19,0);
|
||||
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__csr_mask,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__curr_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__jal_offset,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__PC_next,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__csr_result,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__curr_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__branch_offset,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__jal_dest,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__PC_next,31,0);
|
||||
VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
|
||||
VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
|
||||
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__cycle,63,0);
|
||||
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__instret,63,0);
|
||||
VL_SIG8(Vortex__DOT__fetch_valid[2],0,0);
|
||||
VL_SIG8(Vortex__DOT__f_d_valid[2],0,0);
|
||||
VL_SIG(Vortex__DOT__decode_a_reg_data[2],31,0);
|
||||
VL_SIG(Vortex__DOT__decode_b_reg_data[2],31,0);
|
||||
VL_SIG8(Vortex__DOT__decode_valid[2],0,0);
|
||||
VL_SIG8(Vortex__DOT__decode_thread_mask[2],0,0);
|
||||
VL_SIG(Vortex__DOT__d_e_a_reg_data[2],31,0);
|
||||
VL_SIG(Vortex__DOT__d_e_b_reg_data[2],31,0);
|
||||
VL_SIG8(Vortex__DOT__d_e_valid[2],0,0);
|
||||
VL_SIG(Vortex__DOT__execute_alu_result[2],31,0);
|
||||
VL_SIG(Vortex__DOT__execute_b_reg_data[2],31,0);
|
||||
VL_SIG8(Vortex__DOT__execute_valid[2],0,0);
|
||||
VL_SIG(Vortex__DOT__e_m_alu_result[2],31,0);
|
||||
VL_SIG(Vortex__DOT__e_m_b_reg_data[2],31,0);
|
||||
VL_SIG8(Vortex__DOT__e_m_valid[2],0,0);
|
||||
VL_SIG(Vortex__DOT__memory_alu_result[2],31,0);
|
||||
VL_SIG(Vortex__DOT__memory_mem_result[2],31,0);
|
||||
VL_SIG8(Vortex__DOT__memory_valid[2],0,0);
|
||||
VL_SIG(Vortex__DOT__m_w_alu_result[2],31,0);
|
||||
VL_SIG(Vortex__DOT__m_w_mem_result[2],31,0);
|
||||
VL_SIG8(Vortex__DOT__m_w_valid[2],0,0);
|
||||
VL_SIG(Vortex__DOT__writeback_write_data[2],31,0);
|
||||
VL_SIG(Vortex__DOT__forwarding_src1_fwd_data[2],31,0);
|
||||
VL_SIG(Vortex__DOT__forwarding_src2_fwd_data[2],31,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_zero_valid[2],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_one_valid[2],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__VX_Warp_zero__DOT__valid[2],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__VX_Warp_one__DOT__valid[2],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid[2],0,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__w0_t0_registers[32],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__zero_a_reg_data[2],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__zero_b_reg_data[2],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__one_a_reg_data[2],31,0);
|
||||
};
|
||||
struct {
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__one_b_reg_data[2],31,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__jalrs_thread_mask[2],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__jmprt_thread_mask[2],0,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register[2],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd2_register[2],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[32],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers[32],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__rd1_register[2],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__rd2_register[2],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[32],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[32],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[2],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[2],31,0);
|
||||
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid[2],0,0);
|
||||
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[2],31,0);
|
||||
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid_z[2],0,0);
|
||||
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__alu_result[2],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__a_reg_data[2],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[2],31,0);
|
||||
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__valid[2],0,0);
|
||||
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__alu_result[2],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__mem_result[2],31,0);
|
||||
VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__valid[2],0,0);
|
||||
VL_SIG(Vortex__DOT__vx_writeback__DOT__out_pc_data[2],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[2],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[2],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[2],31,0);
|
||||
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__csr[4096],11,0);
|
||||
};
|
||||
|
||||
// LOCAL VARIABLES
|
||||
// Internals; generally not touched by application code
|
||||
// Anonymous structures to workaround compiler member-count bugs
|
||||
struct {
|
||||
// Begin mtask footprint all:
|
||||
VL_SIG8(__Vtableidx1,2,0);
|
||||
VL_SIG8(__Vclklast__TOP__clk,0,0);
|
||||
VL_SIG8(__Vclklast__TOP__reset,0,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src2_data,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src1_data,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_src2_data,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_src1_data,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result,31,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellout__vx_fetch__out_valid[2],0,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask[2],0,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[2],0,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[2],0,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_thread_mask[2],0,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_valid[2],0,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[2],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[2],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[2],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[2],31,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[2],0,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_write_data[2],31,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_valid[2],0,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[2],0,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[2],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[2],31,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[2],0,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[2],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[2],31,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellout__vx_execute__out_valid[2],0,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[2],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_alu_result[2],31,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellinp__vx_execute__in_valid[2],0,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[2],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[2],31,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[2],0,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[2],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[2],31,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[2],0,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[2],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[2],31,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[2],0,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[2],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[2],31,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_valid[2],0,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_mem_result[2],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_alu_result[2],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[2],31,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellinp__vx_memory__in_valid[2],0,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_rd2[2],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_alu_result[2],31,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[2],0,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[2],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[2],31,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[2],0,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[2],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[2],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_writeback__out_write_data[2],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[2],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[2],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[2],31,0);
|
||||
};
|
||||
struct {
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[2],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[2],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[2],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[2],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[2],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[2],31,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp_zero__out_valid[2],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp_zero__in_thread_mask[2],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp_one__out_valid[2],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp_one__in_thread_mask[2],0,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[32],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data[2],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data[2],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_write_data[2],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src2_fwd_data[2],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src1_fwd_data[2],31,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_valid[2],0,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_one__out_b_reg_data[2],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_one__out_a_reg_data[2],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[32],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_write_data[2],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_src2_fwd_data[2],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_src1_fwd_data[2],31,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_valid[2],0,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[32],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[32],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[32],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[32],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[32],31,0);
|
||||
};
|
||||
static VL_ST_SIG8(__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[8],4,0);
|
||||
|
||||
// INTERNAL VARIABLES
|
||||
// Internals; generally not touched by application code
|
||||
VVortex__Syms* __VlSymsp; // Symbol table
|
||||
|
||||
// PARAMETERS
|
||||
// Parameters marked /*verilator public*/ for use by application code
|
||||
|
||||
// CONSTRUCTORS
|
||||
private:
|
||||
VL_UNCOPYABLE(VVortex); ///< Copying not allowed
|
||||
public:
|
||||
/// Construct the model; called by application code
|
||||
/// The special name may be used to make a wrapper with a
|
||||
/// single model invisible with respect to DPI scope names.
|
||||
VVortex(const char* name="TOP");
|
||||
/// Destroy the model; called (often implicitly) by application code
|
||||
~VVortex();
|
||||
|
||||
// API METHODS
|
||||
/// Evaluate the model. Application must call when inputs change.
|
||||
void eval();
|
||||
/// Simulation complete, run final blocks. Application must call on completion.
|
||||
void final();
|
||||
|
||||
// INTERNAL METHODS
|
||||
private:
|
||||
static void _eval_initial_loop(VVortex__Syms* __restrict vlSymsp);
|
||||
public:
|
||||
void __Vconfigure(VVortex__Syms* symsp, bool first);
|
||||
private:
|
||||
static QData _change_request(VVortex__Syms* __restrict vlSymsp);
|
||||
public:
|
||||
static void _combo__TOP__5(VVortex__Syms* __restrict vlSymsp);
|
||||
static void _combo__TOP__8(VVortex__Syms* __restrict vlSymsp);
|
||||
private:
|
||||
void _ctor_var_reset();
|
||||
public:
|
||||
static void _eval(VVortex__Syms* __restrict vlSymsp);
|
||||
private:
|
||||
#ifdef VL_DEBUG
|
||||
void _eval_debug_assertions();
|
||||
#endif // VL_DEBUG
|
||||
public:
|
||||
static void _eval_initial(VVortex__Syms* __restrict vlSymsp);
|
||||
static void _eval_settle(VVortex__Syms* __restrict vlSymsp);
|
||||
static void _initial__TOP__1(VVortex__Syms* __restrict vlSymsp);
|
||||
static void _sequent__TOP__3(VVortex__Syms* __restrict vlSymsp);
|
||||
static void _sequent__TOP__4(VVortex__Syms* __restrict vlSymsp);
|
||||
static void _sequent__TOP__6(VVortex__Syms* __restrict vlSymsp);
|
||||
static void _sequent__TOP__7(VVortex__Syms* __restrict vlSymsp);
|
||||
static void _settle__TOP__2(VVortex__Syms* __restrict vlSymsp);
|
||||
} VL_ATTR_ALIGNED(128);
|
||||
|
||||
#endif // guard
|
||||
@@ -1,66 +0,0 @@
|
||||
# Verilated -*- Makefile -*-
|
||||
# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
|
||||
#
|
||||
# Execute this makefile from the object directory:
|
||||
# make -f VVortex.mk
|
||||
|
||||
default: VVortex
|
||||
|
||||
### Constants...
|
||||
# Perl executable (from $PERL)
|
||||
PERL = perl
|
||||
# Path to Verilator kit (from $VERILATOR_ROOT)
|
||||
VERILATOR_ROOT = /usr/local/Cellar/verilator/4.010/share/verilator
|
||||
# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
|
||||
SYSTEMC_INCLUDE ?=
|
||||
# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
|
||||
SYSTEMC_LIBDIR ?=
|
||||
|
||||
### Switches...
|
||||
# SystemC output mode? 0/1 (from --sc)
|
||||
VM_SC = 0
|
||||
# Legacy or SystemC output mode? 0/1 (from --sc)
|
||||
VM_SP_OR_SC = $(VM_SC)
|
||||
# Deprecated
|
||||
VM_PCLI = 1
|
||||
# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH)
|
||||
VM_SC_TARGET_ARCH = linux
|
||||
|
||||
### Vars...
|
||||
# Design prefix (from --prefix)
|
||||
VM_PREFIX = VVortex
|
||||
# Module prefix (from --prefix)
|
||||
VM_MODPREFIX = VVortex
|
||||
# User CFLAGS (from -CFLAGS on Verilator command line)
|
||||
VM_USER_CFLAGS = \
|
||||
|
||||
# User LDLIBS (from -LDFLAGS on Verilator command line)
|
||||
VM_USER_LDLIBS = \
|
||||
|
||||
# User .cpp files (from .cpp's on Verilator command line)
|
||||
VM_USER_CLASSES = \
|
||||
test_bench \
|
||||
|
||||
# User .cpp directories (from .cpp's on Verilator command line)
|
||||
VM_USER_DIR = \
|
||||
. \
|
||||
|
||||
|
||||
### Default rules...
|
||||
# Include list of all generated classes
|
||||
include VVortex_classes.mk
|
||||
# Include global rules
|
||||
include $(VERILATOR_ROOT)/include/verilated.mk
|
||||
|
||||
### Executable rules... (from --exe)
|
||||
VPATH += $(VM_USER_DIR)
|
||||
|
||||
test_bench.o: test_bench.cpp
|
||||
$(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
|
||||
|
||||
### Link rules... (from --exe)
|
||||
VVortex: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a
|
||||
$(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) $(SC_LIBS)
|
||||
|
||||
|
||||
# Verilated -*- Makefile -*-
|
||||
Binary file not shown.
@@ -1,3 +0,0 @@
|
||||
// DESCRIPTION: Generated by verilator_includer via makefile
|
||||
#define VL_INCLUDE_OPT include
|
||||
#include "VVortex.cpp"
|
||||
@@ -1,4 +0,0 @@
|
||||
VVortex__ALLcls.o: VVortex__ALLcls.cpp VVortex.cpp VVortex.h \
|
||||
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
|
||||
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h \
|
||||
VVortex__Syms.h
|
||||
Binary file not shown.
@@ -1,3 +0,0 @@
|
||||
// DESCRIPTION: Generated by verilator_includer via makefile
|
||||
#define VL_INCLUDE_OPT include
|
||||
#include "VVortex__Syms.cpp"
|
||||
@@ -1,4 +0,0 @@
|
||||
VVortex__ALLsup.o: VVortex__ALLsup.cpp VVortex__Syms.cpp VVortex__Syms.h \
|
||||
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
|
||||
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h \
|
||||
VVortex.h
|
||||
Binary file not shown.
@@ -1,19 +0,0 @@
|
||||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Symbol table implementation internals
|
||||
|
||||
#include "VVortex__Syms.h"
|
||||
#include "VVortex.h"
|
||||
|
||||
// FUNCTIONS
|
||||
VVortex__Syms::VVortex__Syms(VVortex* topp, const char* namep)
|
||||
// Setup locals
|
||||
: __Vm_namep(namep)
|
||||
, __Vm_didInit(false)
|
||||
// Setup submodule names
|
||||
{
|
||||
// Pointer to top level
|
||||
TOPp = topp;
|
||||
// Setup each module's pointers to their submodules
|
||||
// Setup each module's pointer back to symbol table (for public functions)
|
||||
TOPp->__Vconfigure(this, true);
|
||||
}
|
||||
@@ -1,34 +0,0 @@
|
||||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Symbol table internal header
|
||||
//
|
||||
// Internal details; most calling programs do not need this header
|
||||
|
||||
#ifndef _VVortex__Syms_H_
|
||||
#define _VVortex__Syms_H_
|
||||
|
||||
#include "verilated.h"
|
||||
|
||||
// INCLUDE MODULE CLASSES
|
||||
#include "VVortex.h"
|
||||
|
||||
// SYMS CLASS
|
||||
class VVortex__Syms : public VerilatedSyms {
|
||||
public:
|
||||
|
||||
// LOCAL STATE
|
||||
const char* __Vm_namep;
|
||||
bool __Vm_didInit;
|
||||
|
||||
// SUBCELL STATE
|
||||
VVortex* TOPp;
|
||||
|
||||
// CREATORS
|
||||
VVortex__Syms(VVortex* topp, const char* namep);
|
||||
~VVortex__Syms() {}
|
||||
|
||||
// METHODS
|
||||
inline const char* name() { return __Vm_namep; }
|
||||
|
||||
} VL_ATTR_ALIGNED(64);
|
||||
|
||||
#endif // guard
|
||||
@@ -1 +0,0 @@
|
||||
obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/Cellar/verilator/4.010/bin/verilator_bin /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_alu.v VX_context.v VX_context_slave.v VX_csr_handler.v VX_d_e_reg.v VX_decode.v VX_define.v VX_e_m_reg.v VX_execute.v VX_f_d_reg.v VX_fetch.v VX_forwarding.v VX_m_w_reg.v VX_memory.v VX_register_file.v VX_register_file_master_slave.v VX_register_file_slave.v VX_warp.v VX_writeback.v Vortex.v
|
||||
@@ -1,31 +0,0 @@
|
||||
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
|
||||
C "-Wall -cc Vortex.v --exe test_bench.cpp"
|
||||
S 4608404 12889046060 1553037052 0 1548678579 0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin"
|
||||
S 2785 12890803842 1558067516 0 1558067516 0 "VX_alu.v"
|
||||
S 3486 12890803843 1558067516 0 1558067516 0 "VX_context.v"
|
||||
S 4928 12890803844 1558067516 0 1558067516 0 "VX_context_slave.v"
|
||||
S 1495 12889457987 1554023089 0 1554023089 0 "VX_csr_handler.v"
|
||||
S 5512 12890803845 1558067516 0 1558067516 0 "VX_d_e_reg.v"
|
||||
S 14563 12890803846 1558067516 0 1558067516 0 "VX_decode.v"
|
||||
S 1574 12890803847 1558067516 0 1558067516 0 "VX_define.v"
|
||||
S 4267 12890803848 1558067516 0 1558067516 0 "VX_e_m_reg.v"
|
||||
S 3692 12890803849 1558067516 0 1558067516 0 "VX_execute.v"
|
||||
S 1751 12890803850 1558067516 0 1558067516 0 "VX_f_d_reg.v"
|
||||
S 4619 12890803851 1558067516 0 1558067516 0 "VX_fetch.v"
|
||||
S 6293 12890803852 1558067516 0 1558067516 0 "VX_forwarding.v"
|
||||
S 1866 12890803853 1558067516 0 1558067516 0 "VX_m_w_reg.v"
|
||||
S 4352 12890803854 1558067516 0 1558067516 0 "VX_memory.v"
|
||||
S 1249 12890803855 1558067516 0 1558067516 0 "VX_register_file.v"
|
||||
S 1655 12890803856 1558067516 0 1558067516 0 "VX_register_file_master_slave.v"
|
||||
S 1599 12890803857 1558067516 0 1558067516 0 "VX_register_file_slave.v"
|
||||
S 1686 12890803859 1558067516 0 1558067516 0 "VX_warp.v"
|
||||
S 1568 12890803860 1558067516 0 1558067516 0 "VX_writeback.v"
|
||||
S 18714 12890803861 1558067516 0 1558067516 0 "Vortex.v"
|
||||
T 451065 12890803863 1558067556 0 1558067556 0 "obj_dir/VVortex.cpp"
|
||||
T 20559 12890803864 1558067556 0 1558067556 0 "obj_dir/VVortex.h"
|
||||
T 1800 12890416977 1558067556 0 1558067556 0 "obj_dir/VVortex.mk"
|
||||
T 530 12890416973 1558067556 0 1558067556 0 "obj_dir/VVortex__Syms.cpp"
|
||||
T 711 12890416972 1558067556 0 1558067556 0 "obj_dir/VVortex__Syms.h"
|
||||
T 563 12890416978 1558067556 0 1558067556 0 "obj_dir/VVortex__ver.d"
|
||||
T 0 0 1558067556 0 1558067556 0 "obj_dir/VVortex__verFiles.dat"
|
||||
T 1159 12890416976 1558067556 0 1558067556 0 "obj_dir/VVortex_classes.mk"
|
||||
@@ -1,38 +0,0 @@
|
||||
# Verilated -*- Makefile -*-
|
||||
# DESCRIPTION: Verilator output: Make include file with class lists
|
||||
#
|
||||
# This file lists generated Verilated files, for including in higher level makefiles.
|
||||
# See VVortex.mk for the caller.
|
||||
|
||||
### Switches...
|
||||
# Coverage output mode? 0/1 (from --coverage)
|
||||
VM_COVERAGE = 0
|
||||
# Threaded output mode? 0/1/N threads (from --threads)
|
||||
VM_THREADS = 0
|
||||
# Tracing output mode? 0/1 (from --trace)
|
||||
VM_TRACE = 0
|
||||
|
||||
### Object file lists...
|
||||
# Generated module classes, fast-path, compile with highest optimization
|
||||
VM_CLASSES_FAST += \
|
||||
VVortex \
|
||||
|
||||
# Generated module classes, non-fast-path, compile with low/medium optimization
|
||||
VM_CLASSES_SLOW += \
|
||||
|
||||
# Generated support classes, fast-path, compile with highest optimization
|
||||
VM_SUPPORT_FAST += \
|
||||
|
||||
# Generated support classes, non-fast-path, compile with low/medium optimization
|
||||
VM_SUPPORT_SLOW += \
|
||||
VVortex__Syms \
|
||||
|
||||
# Global classes, need linked once per executable, fast-path, compile with highest optimization
|
||||
VM_GLOBAL_FAST += \
|
||||
verilated \
|
||||
|
||||
# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization
|
||||
VM_GLOBAL_SLOW += \
|
||||
|
||||
|
||||
# Verilated -*- Makefile -*-
|
||||
@@ -1,4 +0,0 @@
|
||||
test_bench.o: ../test_bench.cpp ../test_bench.h ../VX_define.h ../ram.h \
|
||||
VVortex.h \
|
||||
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
|
||||
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h
|
||||
Binary file not shown.
@@ -1,9 +0,0 @@
|
||||
verilated.o: \
|
||||
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.cpp \
|
||||
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h \
|
||||
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_imp.h \
|
||||
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
|
||||
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_heavy.h \
|
||||
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_syms.h \
|
||||
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_sym_props.h \
|
||||
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_config.h
|
||||
Binary file not shown.
@@ -1,7 +0,0 @@
|
||||
# Dynamic Instructions: 222955
|
||||
# of total cycles: 222962
|
||||
# of forwarding stalls: 0
|
||||
# of branch stalls: 0
|
||||
# CPI: 1.00003
|
||||
# time to simulate: 6.95312e-310 milliseconds
|
||||
# GRADE: Failed on test: 4294967295
|
||||
|
||||
@@ -148,7 +148,6 @@ bool Vortex::ibus_driver()
|
||||
|
||||
|
||||
////////////////////// STATS //////////////////////
|
||||
++stats_total_cycles;
|
||||
|
||||
|
||||
if (((((unsigned int)curr_inst) != 0) && (((unsigned int)curr_inst) != 0xffffffff)))
|
||||
@@ -175,10 +174,13 @@ bool Vortex::dbus_driver()
|
||||
// std::cout << "DBUS DRIVER\n" << std::endl;
|
||||
////////////////////// DBUS //////////////////////
|
||||
|
||||
bool did = false;
|
||||
|
||||
for (unsigned curr_th = 0; curr_th < NT; curr_th++)
|
||||
{
|
||||
if ((vortex->out_cache_driver_in_mem_write != NO_MEM_WRITE) && vortex->out_cache_driver_in_valid[curr_th])
|
||||
{
|
||||
did = true;
|
||||
data_write = (uint32_t) vortex->out_cache_driver_in_data[curr_th];
|
||||
addr = (uint32_t) vortex->out_cache_driver_in_address[curr_th];
|
||||
|
||||
@@ -187,6 +189,18 @@ bool Vortex::dbus_driver()
|
||||
std::cerr << (char) data_write;
|
||||
}
|
||||
|
||||
if ((addr >= 0x810002cc) && (addr < 0x810002d0))
|
||||
{
|
||||
int index = (addr - 0x810002cc) / 4;
|
||||
std::cerr << GREEN << "1done[" << index << "] = " << data_write << DEFAULT << "\n";
|
||||
}
|
||||
|
||||
if ((addr >= 0x810059f4) && (addr < 0x810059f4))
|
||||
{
|
||||
int index = (addr - 0x810059f4) / 4;
|
||||
std::cerr << RED << "2done[" << index << "] = " << data_write << DEFAULT << "\n";
|
||||
}
|
||||
|
||||
if (vortex->out_cache_driver_in_mem_write == SB_MEM_WRITE)
|
||||
{
|
||||
data_write = ( data_write) & 0xFF;
|
||||
@@ -208,14 +222,15 @@ bool Vortex::dbus_driver()
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
// printf("----\n");
|
||||
for (unsigned curr_th = 0; curr_th < NT; curr_th++)
|
||||
{
|
||||
|
||||
if ((vortex->out_cache_driver_in_mem_read != NO_MEM_READ) && vortex->out_cache_driver_in_valid[curr_th])
|
||||
{
|
||||
|
||||
|
||||
did = true;
|
||||
addr = (uint32_t) vortex->out_cache_driver_in_address[curr_th];
|
||||
ram.getWord(addr, &data_read);
|
||||
|
||||
@@ -258,6 +273,15 @@ bool Vortex::dbus_driver()
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if (did && (NW > 1))
|
||||
{
|
||||
|
||||
if (NW < NT)
|
||||
{
|
||||
this->stats_total_cycles += NT % (NW -1);
|
||||
}
|
||||
}
|
||||
// printf("******\n");
|
||||
|
||||
|
||||
@@ -294,7 +318,6 @@ bool Vortex::simulate(std::string file_to_simulate)
|
||||
unsigned curr_inst;
|
||||
unsigned new_PC;
|
||||
|
||||
int cycle = 0;
|
||||
// while (this->stop && (!(stop && (counter > 5))))
|
||||
// {
|
||||
|
||||
@@ -360,10 +383,10 @@ bool Vortex::simulate(std::string file_to_simulate)
|
||||
counter = 0;
|
||||
}
|
||||
|
||||
cycle++;
|
||||
++stats_total_cycles;
|
||||
}
|
||||
|
||||
std::cerr << "Total Cycles: " << cycle << "\n";
|
||||
std::cerr << "New Total Cycles: " << (this->stats_total_cycles) << "\n";
|
||||
|
||||
uint32_t status;
|
||||
ram.getWord(0, &status);
|
||||
|
||||
Reference in New Issue
Block a user