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Blaise Tine e1197575e6 cutcp
2019-11-25 14:07:51 -05:00
benchmarks
cutcp
2019-11-25 14:07:51 -05:00
emulator
VCD for power
2019-11-21 23:25:51 -05:00
models/memory
Added rf2_32x19_wm0 again
2019-11-11 14:28:45 -05:00
rtl
Fixed GPR Stage to be Generic when ASIC is defined
2019-11-22 09:20:20 -05:00
runtime
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
2019-11-25 02:52:22 -05:00
rvvector
Merge remote-tracking branch 'refs/remotes/origin/master'
2019-11-24 09:00:43 -05:00
simX
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
2019-11-25 02:52:22 -05:00
syn
Started synthesis script
2019-11-22 00:32:19 -05:00
.DS_Store
ram stdint + Quartus Files
2019-06-11 21:13:30 -07:00
.gitignore
migrated 100% to modelsim
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README.md
Added a README
2019-03-22 04:29:24 -04:00
results.txt
Less expensive but slower fetch logic
2019-05-05 22:55:47 -04:00
sftp-config.json
Started synthesis script
2019-11-22 00:32:19 -05:00
TODO
TODO update
2019-11-07 20:52:36 -05:00

README.md

Vortex RISC-V GPGPU

Vortex currently supported RV32IM.

./Kernel is a demo of exposing the warps and threads to a program. (Stable)

./emulator is an emulator for RV32IM with warp and thread support. (Stable)

./rtl is verilog for the processor. Currently supports RV32IM and passes all tests.

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