felsabbagh3 0e0b326b31 Removed bank Hazard Signals

2020-04-02 19:19:00 -07:00

..

quartus

synthesis fixes

2020-03-05 06:58:51 -05:00

VX_bank.v

Removed bank Hazard Signals

2020-04-02 19:19:00 -07:00

VX_cache_config.v

MULTICORE WITH L2 WORKING

2020-03-09 01:17:11 -07:00

VX_cache_core_req_bank_sel.v

MULTICORE WITH L2 WORKING

2020-03-09 01:17:11 -07:00

VX_cache_dfq_queue.v

Cache Working on Mem Copy

2020-03-08 01:55:15 -08:00

VX_cache_dram_req_arb.v

Fixed pulling signals from different stages

2020-03-29 18:17:01 -07:00

VX_cache_miss_resrv.v

Another reset issue...

2020-03-29 16:06:13 -07:00

VX_cache_req_queue.v

b/unb error

2020-03-29 16:09:48 -07:00

VX_cache_wb_sel_merge.v

L3 and CLUSTRING WORKS

2020-03-10 02:41:47 -07:00

VX_cache.v

Added Proper Handshaking to Everything and Fixed a Couple of Bugs

2020-03-29 02:11:14 -07:00

VX_dcache_llv_resp_bank_sel.v

Fixed all Cache Warnings

2020-03-07 14:34:05 -08:00

VX_fill_invalidator.v

All cache bugs fixed - Handshaking

2020-03-28 21:43:02 -07:00

VX_mrv_queue.v

Cache Working on Mem Copy

2020-03-08 01:55:15 -08:00

VX_snp_fwd_arb.v

fixed Modelsim build errors

2020-03-26 03:54:23 -04:00

VX_tag_data_access.v

Demo SOC W=8, T=4 Passing

2020-03-30 22:17:38 -07:00

VX_tag_data_structure.v

Demo SOC W=8, T=4 Passing

2020-03-30 22:17:38 -07:00