Another reset issue...

rtl/VX_cache/VX_cache_miss_resrv.v

@@ -132,6 +132,9 @@ module VX_cache_miss_resrv
 				ready_table <= 0;
 				addr_table  <= 0;
 				pc_table    <= 0;
+				size        <= 0;
+				head_ptr    <= 0;
+				tail_ptr    <= 0;
 			end else begin
 				if (mrvq_push) begin
 					valid_table[enqueue_index]    <= 1;

rtl/VX_cache/VX_cache_req_queue.v

@@ -175,6 +175,7 @@ module VX_cache_req_queue
 
 	always @(posedge clk) begin
 		if (reset) begin
+			updated_valids    <= 0;
  			use_per_valids    <= 0;
 			use_per_addr      <= 0;
 			use_per_writedata <= 0;