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tensor: Instantiate correct fake tcore module according to parameter

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This has to align with what the verilog source actually uses.
This commit is contained in:
Hansung Kim
2024-10-27 18:48:44 -07:00
parent 13b9577723
commit 0ba61aabb6
1 changed files with 31 additions and 20 deletions
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51
src/main/scala/radiance/tile/RadianceTile.scala
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@@ -851,26 +851,37 @@ class RadianceTileModuleImp(outer: RadianceTile)
// synthesis runs, although these will likely be optimized-out if the inputs // synthesis runs, although these will likely be optimized-out if the inputs
// are tied to low. // are tied to low.
val tensorNumSourceIds = (1 << outer.tensorTagWidth) if (outer.radianceParams.core.tensorCoreDecoupled) {
val tensor = Module(new radiance.core.TensorCoreDecoupled( val tensorNumSourceIds = (1 << outer.tensorTagWidth)
8, 8, half = true, tensorNumSourceIds)) val tensor = Module(new radiance.core.TensorCoreDecoupled(
tensor.io.initiate.valid := false.B 8, 8, half = true, tensorNumSourceIds))
tensor.io.initiate.bits := DontCare tensor.io.initiate.valid := false.B
tensor.io.respA.valid := false.B tensor.io.initiate.bits := DontCare
tensor.io.respA.bits := DontCare tensor.io.respA.valid := false.B
tensor.io.respB.valid := false.B tensor.io.respA.bits := DontCare
tensor.io.respB.bits := DontCare tensor.io.respB.valid := false.B
tensor.io.respC := DontCare tensor.io.respB.bits := DontCare
tensor.io.reqA.ready := false.B tensor.io.respC := DontCare
tensor.io.reqB.ready := false.B tensor.io.reqA.ready := false.B
tensor.io.writeback.ready := false.B tensor.io.reqB.ready := false.B
tensor.io.writeback.ready := false.B
val dpu = Module(new radiance.core.TensorDotProductUnit(8, half = true)) } else {
dpu.io.in.valid := false.B if (outer.radianceParams.core.tensorCoreFP16) {
dpu.io.in.bits.a := DontCare val dpu = Module(new radiance.core.TensorDotProductUnit(4, half = true))
dpu.io.in.bits.b := DontCare dpu.io.in.valid := false.B
dpu.io.in.bits.c := DontCare dpu.io.in.bits.a := DontCare
dpu.io.stall := false.B dpu.io.in.bits.b := DontCare
dpu.io.in.bits.c := DontCare
dpu.io.stall := false.B
} else {
val dpu = Module(new radiance.core.TensorDotProductUnit(2, half = false))
dpu.io.in.valid := false.B
dpu.io.in.bits.a := DontCare
dpu.io.in.bits.b := DontCare
dpu.io.in.bits.c := DontCare
dpu.io.stall := false.B
}
}
// // RoCC // // RoCC
// if (outer.roccs.size > 0) { // if (outer.roccs.size > 0) {