Hansung Kim 0ba61aabb6 tensor: Instantiate correct fake tcore module according to parameter ...

This has to align with what the verilog source actually uses.

2024-10-27 18:48:44 -07:00

radpie @ 493b8e10a5

Bump radpie

2024-01-30 18:01:19 -08:00

src

tensor: Instantiate correct fake tcore module according to parameter

2024-10-27 18:48:44 -07:00

.gitignore

Don't gitignore *.v

2024-01-19 16:09:41 -08:00

.gitmodules

Use ssh for vortex remote path

2024-03-22 19:47:26 -07:00

.scalafix.conf

add back purged files

2024-01-17 16:40:13 -08:00

.scalafmt.conf

Add .scalafmt.conf

2023-03-27 14:38:02 -07:00

build.sbt

add back purged files

2024-01-17 16:40:13 -08:00

LICENSE.Berkeley

add back purged files

2024-01-17 16:40:13 -08:00

LICENSE.SiFive

add back purged files

2024-01-17 16:40:13 -08:00

radiance.mk

radiance.mk: Remove SMEM_LOG_SIZE override

2024-09-10 15:38:12 -07:00

Description

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1.2 MiB

Languages

Scala 91.6%

C++ 3.9%

Verilog 3.6%

Makefile 0.9%