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Add TL client node to MemTraceDriver

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This commit is contained in:
Hansung Kim
2023-02-27 23:35:14 -08:00
parent a06b5faa3c
commit 24f4ee93ac
1 changed files with 31 additions and 20 deletions
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35
src/main/scala/tilelink/Coalescing.scala
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@@ -8,14 +8,15 @@ import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._ import freechips.rocketchip.diplomacy._
import freechips.rocketchip.unittest._ import freechips.rocketchip.unittest._
class CoalescingUnit(txns: Int = 5000)(implicit p: Parameters) extends LazyModule { class CoalescingUnit(txns: Int = 5000)(implicit p: Parameters)
extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns)) val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("Xbar")) val model = LazyModule(new TLRAMModel("Xbar"))
val xbar = LazyModule(new TLXbar) val xbar = LazyModule(new TLXbar)
xbar.node := TLDelayer(0.1) := model.node := fuzz.node xbar.node := TLDelayer(0.1) := model.node := fuzz.node
(0 until 1) foreach { n => (0 until 1) foreach { n =>
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) val ram = LazyModule(new TLRAM(AddressSet(0x0 + 0x400 * n, 0x3ff)))
ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
} }
@@ -25,20 +26,31 @@ class CoalescingUnit(txns: Int = 5000)(implicit p: Parameters) extends LazyModul
} }
} }
class MemTraceDriver(implicit p: Parameters) extends Module with UnitTestModule { class MemTraceDriver(implicit p: Parameters) extends LazyModule {
// TODO: generate TL request here
// testchipip provides TLHelper.makeClientNode convenience wrapper for this.
val clients = Seq(
TLMasterParameters.v1(
name = "MemTraceDriver",
sourceId = IdRange(0, 1 /*FIXME*/ )
)
)
val node = TLClientNode(Seq(TLMasterPortParameters.v1(clients)))
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
val sim = Module(new SimMemTrace) val sim = Module(new SimMemTrace)
sim.io.clock := clock sim.io.clock := clock
sim.io.reset := reset.asBool sim.io.reset := reset.asBool
sim.io.trace_read.ready := true.B sim.io.trace_read.ready := true.B
when (sim.io.trace_read.valid) { when(sim.io.trace_read.valid) {
println("sim.io.valid!") println("sim.io.valid!")
} }
// TODO: generate TL request here
// we're finished when there is no more memtrace to read // we're finished when there is no more memtrace to read
io.finished := !sim.io.trace_read.valid io.finished := !sim.io.trace_read.valid
}
} }
class SimMemTrace extends BlackBox with HasBlackBoxResource { class SimMemTrace extends BlackBox with HasBlackBoxResource {
@@ -58,12 +70,11 @@ class SimMemTrace extends BlackBox with HasBlackBoxResource {
addResource("/csrc/SimMemTrace.cc") addResource("/csrc/SimMemTrace.cc")
} }
class CoalescingUnitTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) class CoalescingUnitTest(txns: Int = 5000, timeout: Int = 500000)(implicit
extends UnitTest(timeout) { p: Parameters
// val dut = Module(LazyModule(new CoalescingUnit(txns)).module) ) extends UnitTest(timeout) {
// dut.io.start := io.start val coal = Module(LazyModule(new CoalescingUnit(txns)).module)
val driver = Module(LazyModule(new MemTraceDriver).module)
val driver = Module(new MemTraceDriver)
driver.io.start := io.start driver.io.start := io.start
io.finished := driver.io.finished io.finished := driver.io.finished