wu-arch/radiance
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge branch 'main' of https://github.com/ucb-bar/radiance into main

Browse Source
This commit is contained in:
Richard Yan
2024-04-17 18:09:52 -07:00
parent bb8575252e 3b9f538aa2
commit 3e0d87e1dd
2 changed files with 5 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
radiance.mk
View File

@@ -2,18 +2,19 @@
# extra variables/targets ingested by the chipyard make system
##############################################################
RADPIE_SRC_DIR = $(base_dir)/generators/radiance/radpie
RADPIE_BUILD_DIR = $(RADPIE_SRC_DIR)/target/release
##################################################################
# THE FOLLOWING MUST BE += operators
##################################################################
RADPIE_SRC_DIR = $(base_dir)/generators/radiance/radpie
RADPIE_BUILD_DIR = $(RADPIE_SRC_DIR)/target/release
# EXTRA_SIM_REQS += radpie
EXTRA_SIM_LDFLAGS += -L$(RADPIE_BUILD_DIR) -Wl,-rpath,$(RADPIE_BUILD_DIR) -lradpie
EXTRA_SIM_PREPROC_DEFINES += \
+define+SIMULATION \
+define+GPR_RESET \
+define+GPR_DUPLICATED \
+define+LSU_DUP_DISABLE \
+define+DBG_TRACE_CORE_PIPELINE_VCS \
+define+PERF_ENABLE \

1
src/main/scala/radiance/tile/VortexCore.scala
View File

@@ -176,6 +176,7 @@ class Vortex(tile: RadianceTile)(implicit p: Parameters)
addResource("/vsrc/vortex/hw/rtl/core/VX_lsu_unit.sv")
addResource("/vsrc/vortex/hw/rtl/core/VX_muldiv_unit.sv")
addResource("/vsrc/vortex/hw/rtl/core/VX_operands.sv")
addResource("/vsrc/vortex/hw/rtl/core/VX_operands_dup.sv")
addResource("/vsrc/vortex/hw/rtl/core/VX_pending_instr.sv")
addResource("/vsrc/vortex/hw/rtl/core/VX_schedule.sv")
addResource("/vsrc/vortex/hw/rtl/core/VX_scoreboard.sv")