radiance.mk: Add target that copies Vortex verilog sources
This works in conjunction with the common.mk fix that prevents rebuilding Chipyard jar on every .sv file update.
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35
radiance.mk
35
radiance.mk
@@ -2,6 +2,7 @@
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# extra variables/targets ingested by the chipyard make system
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# extra variables/targets ingested by the chipyard make system
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##############################################################
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##############################################################
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VORTEX_SRC_DIR = $(base_dir)/generators/radiance/src/main/resources/vsrc/vortex
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RADPIE_SRC_DIR = $(base_dir)/generators/radiance/radpie
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RADPIE_SRC_DIR = $(base_dir)/generators/radiance/radpie
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RADPIE_BUILD_DIR = $(RADPIE_SRC_DIR)/target/release
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RADPIE_BUILD_DIR = $(RADPIE_SRC_DIR)/target/release
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@@ -10,7 +11,7 @@ RADPIE_BUILD_DIR = $(RADPIE_SRC_DIR)/target/release
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##################################################################
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##################################################################
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# EXTRA_SIM_REQS += radpie
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# EXTRA_SIM_REQS += radpie
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EXTRA_SIM_LDFLAGS += -L$(RADPIE_BUILD_DIR) -Wl,-rpath,$(RADPIE_BUILD_DIR) -lradpie
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# EXTRA_SIM_LDFLAGS += -L$(RADPIE_BUILD_DIR) -Wl,-rpath,$(RADPIE_BUILD_DIR) -lradpie
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EXTRA_SIM_PREPROC_DEFINES += \
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EXTRA_SIM_PREPROC_DEFINES += \
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+define+SIMULATION \
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+define+SIMULATION \
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+define+GPR_RESET \
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+define+GPR_RESET \
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@@ -33,3 +34,35 @@ EXTRA_SIM_PREPROC_DEFINES += \
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.PHONY: radpie
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.PHONY: radpie
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radpie:
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radpie:
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cd $(RADPIE_SRC_DIR) && cargo build --release
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cd $(RADPIE_SRC_DIR) && cargo build --release
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EXTRA_SIM_REQS += vortex_vsrc
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# doesn't work if we use $(call lookup_srcs) from common.mk, the variable
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# doesn't expand somehow
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VORTEX_VLOG_SOURCES := $(shell fd -L -t f -e "sv" -e "vh" -e "v" . $(VORTEX_SRC_DIR))
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# VORTEX_COLLATERAL := $(patsubst $(VORTEX_SRC_DIR)%,$(GEN_COLLATERAL_DIR)%,$(VORTEX_VLOG_SOURCES))
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# check if expanded
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# $(info VORTEX_VLOG_SOURCES: $(VORTEX_VLOG_SOURCES))
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# For every Vortex verilog source file, if there's a matching file in
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# gen-collateral/, copy them over. This is a hacky way to ensure the changes
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# in the verilog sources are reflected before Verilator/VCS kicks in. The
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# matching with gen-collateral/ is there to prevent unnecessarily copying
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# unused source files e.g. third-party libraries.
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#
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# This assumes that the fix is applied to common.mk, where it does not trigger
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# chipyard jar rebuild when verilog sources are changed.
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vortex_vsrc: $(VORTEX_VLOG_SOURCES)
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@for file in $(VORTEX_VLOG_SOURCES); do \
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filename=$$(basename "$$file"); \
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if [ -f $(GEN_COLLATERAL_DIR)/$$filename ]; then \
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cp -u -v "$$file" $(GEN_COLLATERAL_DIR); \
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fi; \
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done
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touch $@
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sentinel: $(VORTEX_VLOG_SOURCES)
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touch $@
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.PHONY: print
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print:
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@echo $(VORTEX_COLLATERAL)
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