Merge branch 'main' of https://github.com/ucb-bar/radiance into main

radiance.mk

@@ -20,13 +20,13 @@ EXTRA_SIM_PREPROC_DEFINES += \
 	+define+ICACHE_DISABLE +define+DCACHE_DISABLE \
 	+define+GBAR_ENABLE \
 	+define+GBAR_CLUSTER_ENABLE \
-	+define+FPU_FPNEW \
-	+define+EXT_T_DISABLE \
-	+define+NUM_BARRIERS=8 \
-	+define+NUM_CORES=2 +define+NUM_THREADS=8 +define+NUM_WARPS=8
-	# Can't increase this to above 14, since the binary accesses 0xff0040..
-	# which is unmapped to any memory
-	# +define+SMEM_LOG_SIZE=14 \
+	+define+NUM_FPU_BLOCKS=2 \
+	+define+NUM_BARRIERS=4 \
+	+define+NUM_LSU_LANES=4 \
+	+define+NUM_CORES=1 +define+NUM_THREADS=32 +define+NUM_WARPS=4
+	# +define+EXT_T_DISABLE \
+	# +define+FPU_FPNEW \
+	# +define+SMEM_LOG_SIZE=15 \
 
 # cargo handles building of Rust files all on its own, so make this a PHONY
 # target to run cargo unconditionally

src/main/scala/radiance/tile/RadianceTile.scala

@@ -193,9 +193,12 @@ class RadianceTile private (
   }
   val imemTagWidth = UUID_WIDTH + NW_WIDTH
 
-  // val LSUQ_SIZE = 4 * numWarps * (numCoreLanes / numLsuLanes)
-  // assert(LSUQ_SIZE == p(SIMTCoreKey).get.nSrcIds)
-  val LSUQ_SIZE = p(SIMTCoreKey).get.nSrcIds
+  require(numWarps >= numLsuLanes,
+          s"Vortex core requires numWarps (${numWarps}) >= numLsuLanes (${numLsuLanes})")
+  val LSUQ_SIZE = 8 * (numCoreLanes / numLsuLanes)
+  require(LSUQ_SIZE == p(SIMTCoreKey).get.nSrcIds,
+          s"LSUQ_SIZE (${LSUQ_SIZE}) != nSrcIds (${p(SIMTCoreKey).get.nSrcIds})"
+          + " which can result in TileLink srcId underutilization")
   val LSUQ_TAG_BITS = log2Ceil(LSUQ_SIZE) + 1 /*DCACHE_BATCH_SEL_BITS*/
   val dmemTagWidth = UUID_WIDTH + LSUQ_TAG_BITS
   // dmem and smem shares the same tag width, DCACHE_NOSM_TAG_WIDTH