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Add chisel-generated verilog for dpu

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This commit is contained in:
Hansung Kim
2024-05-29 13:33:23 -07:00
parent 4a43d0126d
commit d34c5836a8
2 changed files with 1343 additions and 0 deletions
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1341
src/main/resources/vsrc/TensorDotProductUnit.sv Normal file
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2
src/main/scala/radiance/tile/VortexCore.scala
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@@ -329,6 +329,8 @@ class Vortex(tile: RadianceTile)(implicit p: Parameters)
addResource("/vsrc/vortex/hw/rtl/fpu/VX_fpu_fpnew.sv")
addResource("/vsrc/vortex/hw/rtl/core/VX_fpu_unit.sv")
addResource("/vsrc/TensorDotProductUnit.sv")
// fpnew
// compile order matters; package definitions (ex. fpnew_pkg) should be
// compiled before all the other modules that reference them. They are added