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fix sbus location

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This commit is contained in:
Richard Yan
2024-04-20 03:07:26 -07:00
parent 3e0d87e1dd
commit e08bf2c2c9
1 changed files with 2 additions and 1 deletions
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3
src/main/scala/radiance/memory/CanHaveMemtraceCore.scala
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@@ -1,7 +1,7 @@
package radiance.memory package radiance.memory
import freechips.rocketchip.diplomacy.LazyModule import freechips.rocketchip.diplomacy.LazyModule
import freechips.rocketchip.subsystem.BaseSubsystem import freechips.rocketchip.subsystem._
import org.chipsalliance.cde.config.Parameters import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tilelink._ import freechips.rocketchip.tilelink._
@@ -23,6 +23,7 @@ trait CanHaveMemtraceCore { this: BaseSubsystem =>
val numLanes = simtParam.nMemLanes val numLanes = simtParam.nMemLanes
val filename = param.tracefilename val filename = param.tracefilename
val sbus = locateTLBusWrapper(SBUS)
// Need to explicitly generate clock domain; see rocket-chip 8881ccd // Need to explicitly generate clock domain; see rocket-chip 8881ccd
val memtracerDomain = sbus.generateSynchronousDomain val memtracerDomain = sbus.generateSynchronousDomain
memtracerDomain { memtracerDomain {