Hansung Kim
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664959f723
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Parameterize SimMemTrace Verilog module to number of threads
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2023-03-03 16:16:07 -08:00 |
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Hansung Kim
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44cf6fbb2f
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Update SimMemTrace csrc from submodule
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2023-03-03 16:14:11 -08:00 |
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Hansung Kim
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b57c0e2b7d
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SimMemTrace: parse batch instead of at every cycle
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2023-03-02 17:24:36 -08:00 |
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Hansung Kim
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24f4ee93ac
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Add TL client node to MemTraceDriver
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2023-02-27 23:35:14 -08:00 |
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Hansung Kim
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a06b5faa3c
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Wrap memtrace DPI module with a Chisel driver module
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2023-02-27 19:55:22 -08:00 |
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Hansung Kim
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9025729c0e
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Emit address in addition to cycle
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2023-02-27 17:36:54 -08:00 |
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Hansung Kim
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0ebaed5f1b
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Communicate trace cycle data from C++ to Chisel
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2023-02-27 14:40:49 -08:00 |
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Hansung Kim
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72de4bca66
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Initial parsing of memory trace file in C++
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2023-02-27 13:47:30 -08:00 |
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Hansung Kim
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80e4b5c734
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Set up simple DPI for trace-driven testing
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2023-02-26 20:39:19 -08:00 |
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Hansung Kim
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5bf8bb8217
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Add empty unit test for coalescing unit
copied over from WithTLXbarUnitTests
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2023-02-22 16:42:18 -08:00 |
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Huy Vo
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1b733e7cf0
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Merge branch 'master' of github.com:ucb-bar/riscv-rocket
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2012-03-13 12:34:39 -07:00 |
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Andrew Waterman
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2607153b67
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Merge branch 'master' of github.com:ucb-bar/riscv-rocket
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2012-03-09 02:08:55 -08:00 |
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Yunsup Lee
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4f00bcc760
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Merge branch 'master' of github.com:ucb-bar/riscv-rocket
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2012-02-29 17:12:02 -08:00 |
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Huy Vo
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0fd777f480
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Merge branch 'master' of github.com:ucb-bar/riscv-rocket
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2012-02-26 17:24:23 -08:00 |
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Andrew Waterman
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71c8d3fd41
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reorganize directory structure
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2012-02-08 15:13:08 -08:00 |
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