Hansung Kim
ceb7ee79fe
Don't gitignore *.v
2024-01-19 16:09:41 -08:00
Hansung Kim
737f24fd77
scalafmt
2024-01-19 15:16:37 -08:00
Hansung Kim
fec3d61dd6
Decrease imemSourceWidth to 4
2024-01-18 22:16:22 -08:00
Hansung Kim
0fd4d0a76f
Split IO for lookup and dealloc in InflightTable
...
The usage of `lookup` and `lookupSourceId` ports were being conflated in
terms of table lookup and dealloc. Now `lookupSourceId` solely controls
lookup operation and vice versa. This simplifies pipeline reg logic in
uncoalescer.
2024-01-18 22:10:06 -08:00
Hansung Kim
9ae1d9c392
Put a pipeline stage at uncoalescer
...
... to cut timing after inflight table lookup & before
splitting/enqueueing logic.
2024-01-18 21:34:02 -08:00
Hansung Kim
7e906a39fb
Reduce default respQueueDepth to 2
2024-01-18 19:22:59 -08:00
Hansung Kim
95dcecbe03
Fix uncoalesced response being dropped
...
Need to use fire instead of valid so that the uncoalescing /
inflighttable freeing logic happens exactly once at the fire time.
FIXME: might result in long ready chain that goes from TL-D port all the
way to the response queues.
2024-01-18 18:50:43 -08:00
Hansung Kim
b1a37d0dda
Streamline upstream flow with regards to CoalSourceGen
...
CoalescerSourceGen was prematurely reclaiming sourceIds in the presence
of coalResp backpressure, since it was not referring to coalResp.fire
and instead setting ready to always-true. With this change
CoalSourceGen properly propagates both downstream and upstream
backpressure.
2024-01-18 18:15:18 -08:00
Hansung Kim
086b2a5398
Clean up uncoalescer -> respQueue doc
2024-01-18 18:12:49 -08:00
Hansung Kim
46f5e8b920
Disable force assert for RespQueue block
2024-01-18 18:10:33 -08:00
Hansung Kim
2b8ef4cb30
Create coalResp backpressure when response queues are full
...
... which causes the uncoalescer to lock up, so we shouldn't accept
further coalescer responses.
2024-01-18 01:09:28 -08:00
Hansung Kim
eeb92da8a1
Fix InFlightTable lookup assert
2024-01-18 01:07:49 -08:00
Hansung Kim
e96836c190
Fix inflightCounter debug counter
2024-01-18 01:06:28 -08:00
Hansung Kim
138e83b68a
Assert coreWriteReqQueue is never full in VortexCache
2024-01-18 01:05:23 -08:00
Richard Yan
e53c3fed9b
add back purged files
2024-01-17 16:40:13 -08:00
Hansung Kim
7914607304
Bump vortex with IBUF/LSUQ size change
2024-01-16 23:54:39 -08:00
Hansung Kim
37d2af5478
Reflect upstream rocket-chip changes
...
* hartId -> tileId
* TileCrossingParamsLike -> HierarchicalElementCrossingParamsLike
* don't use bus_error_unit
2024-01-16 23:44:57 -08:00
Hansung Kim
cd1022c608
Remove use of HasTiles to reflect upstream change
2024-01-16 22:59:56 -08:00
Hansung Kim
132742ea88
Distinguish LSU lanes from SIMD lanes and elaborate tag width logic
2024-01-16 22:20:16 -08:00
Richard Yan
263f00baed
Merge remote-tracking branch 'origin/vortex2' into restructure
2024-01-16 17:49:41 -08:00
Richard Yan
dea005a179
incorporate vortex2
2024-01-16 17:41:33 -08:00
Richard Yan
f9b7e9fbe4
restructure from rocket-chip to radiance
2024-01-16 16:21:50 -08:00
Richard Yan
c742a13c1e
restructure: initial filter pass
2024-01-11 10:08:43 -08:00
Hansung Kim
9e1ddfaeb9
Bump vortex with IO flattening
2024-01-04 01:35:30 -08:00
Hansung Kim
51e17e709b
Flatten smem bundle of Vortex core IO into 1-D arrays
2024-01-04 00:53:23 -08:00
Hansung Kim
60cd72a9d6
Flatten dmem bundle of Vortex core IO into 1-D arrays
2024-01-04 00:38:23 -08:00
Hansung Kim
773cfcbd6e
Bump vortex for external smem
2024-01-01 14:27:49 -08:00
Hansung Kim
8c12c7af16
Instantiate multiple TLRAMs as sharedmem banks
2024-01-01 12:49:23 -08:00
Hansung Kim
95e05f5457
Connect smem core IO to TL with translation
2024-01-01 02:24:57 -08:00
Hansung Kim
15c3c55cb6
Make empty sharedmem diplomacy nodes
2024-01-01 00:46:01 -08:00
Hansung Kim
cb2bc8cc0a
Rename VortexBank -> VortexCache
2024-01-01 00:08:25 -08:00
Hansung Kim
65446946be
Bump vortex
2023-12-10 05:58:21 -08:00
Hansung Kim
efac9b7d0b
Better logic for {imem,dmem}TagWidth
2023-12-10 05:58:00 -08:00
Zekai Lin
ca57c8d6a3
TLFragmenter bug fix
2023-12-09 20:27:13 -08:00
Hansung Kim
2879108804
Accept coalescer enable at WithCoalescer config
2023-12-01 19:01:06 -08:00
Hansung Kim
4eb9973b2c
Attempt to replicate bitwidth logic for dmem/imem tag
2023-11-29 15:13:17 -08:00
Hansung Kim
2bdaf3a0a8
Fix undefined {MEM,WORD}_ADDR_SIZE
2023-11-28 22:49:48 -08:00
Hansung Kim
0589b310f1
Add missing parameters for VX_cache_top
2023-11-28 20:32:49 -08:00
Hansung Kim
6248926b47
Remove icache-specific address set and naming
2023-11-28 20:08:46 -08:00
Hansung Kim
74fe530105
Enable configuring MSHR size from Chisel
2023-11-28 19:55:23 -08:00
Hansung Kim
f8d7169d19
Delete old addResource for vortex v1
2023-11-28 19:44:02 -08:00
Hansung Kim
4f274af363
Bump vortex with way_idx revert
2023-11-28 19:34:32 -08:00
Hansung Kim
4efe9cb93f
Instantiate separate VortexL1Cache for imem and dmem
2023-11-28 19:22:11 -08:00
Hansung Kim
0d60180d0d
Change NUM_WAYS from 1 to 4
...
NUM_WAYS = 1 seem to be broken in Vortex. This makes sgemm test pass
2023-11-28 18:43:25 -08:00
Hansung Kim
d45cf835cf
Remove dedicated icache bank from VortexBank
2023-11-28 18:42:58 -08:00
Hansung Kim
b66be6c3ae
Respect VX_cache's MEM_TAG_WIDTH; rename coalToVxCacheNode
2023-11-28 16:54:50 -08:00
Hansung Kim
c5e37dd3b8
Rename l2ReqSourceGenSize -> memSideSourceIds
2023-11-28 14:55:52 -08:00
Hansung Kim
bd1aaaccfe
Bump vortex with trace and CSR fix
2023-11-28 12:52:23 -08:00
Hansung Kim
f187291a9c
VortexBank: Update addResource for vortex2; WIP fix params
2023-11-28 12:51:34 -08:00
Hansung Kim
8ed82e8261
Remove unclear size width requirement in tl adapter
2023-11-27 16:42:07 -08:00
