66 lines
2.6 KiB
Makefile
66 lines
2.6 KiB
Makefile
##############################################################
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# extra variables/targets ingested by the chipyard make system
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##############################################################
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VORTEX_SRC_DIR = $(base_dir)/generators/radiance/src/main/resources/vsrc/vortex
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RADPIE_SRC_DIR = $(base_dir)/generators/radiance/radpie
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RADPIE_BUILD_DIR = $(RADPIE_SRC_DIR)/target/release
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##################################################################
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# THE FOLLOWING MUST BE += operators
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##################################################################
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# EXTRA_SIM_REQS += radpie
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# EXTRA_SIM_LDFLAGS += -L$(RADPIE_BUILD_DIR) -Wl,-rpath,$(RADPIE_BUILD_DIR) -lradpie
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ifeq ($(shell echo $(CONFIG) | grep -E "SynConfig$$"),$(CONFIG))
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EXTRA_SIM_PREPROC_DEFINES += +define+SYNTHESIS +define+NDEBUG +define+DPI_DISABLE
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endif
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EXTRA_SIM_PREPROC_DEFINES += \
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+define+SIMULATION \
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+define+GPR_RESET \
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+define+GPR_DUPLICATED \
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+define+DBG_TRACE_CORE_PIPELINE_VCS \
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+define+PERF_ENABLE \
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+define+ICACHE_DISABLE +define+DCACHE_DISABLE \
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+define+GBAR_ENABLE \
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+define+GBAR_CLUSTER_ENABLE \
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+define+FPU_FPNEW
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# +define+LSU_DUP_DISABLE \
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VCS_NONCC_OPTS += +vcs+initreg+random
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# cargo handles building of Rust files all on its own, so make this a PHONY
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# target to run cargo unconditionally
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.PHONY: radpie
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radpie:
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cd $(RADPIE_SRC_DIR) && cargo build --release
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EXTRA_SIM_REQS += vortex_vsrc.$(CONFIG)
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# below manipulation of VORTEX_VLOG_SOURCES doesn't work if we try to reuse
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# $(call lookup_srcs) from common.mk, the variable doesn't expand somehow
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ifeq ($(shell which fd 2> /dev/null),)
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VORTEX_VLOG_SOURCES := $(shell find -L $(VORTEX_SRC_DIR) -type f -iname "*.sv" -o -iname "*.vh" -o -iname "*.v")
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else
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VORTEX_VLOG_SOURCES := $(shell fd -L -t f -e "sv" -e "vh" -e "v" . $(VORTEX_SRC_DIR))
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endif
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# VORTEX_COLLATERAL := $(patsubst $(VORTEX_SRC_DIR)%,$(GEN_COLLATERAL_DIR)%,$(VORTEX_VLOG_SOURCES))
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# check if expanded
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# $(info VORTEX_VLOG_SOURCES: $(VORTEX_VLOG_SOURCES))
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# For every Vortex verilog source file, if there's a matching file in
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# gen-collateral/, copy them over. This is a hacky way to ensure the changes
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# in the verilog sources are reflected before Verilator/VCS kicks in. This is
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# necessary when common.mk does not trigger chipyard jar rebuild upon verilog
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# source updates, in which case we need to manually ensure the up-to-date-ness
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# of gen-collateral/.
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vortex_vsrc.$(CONFIG): $(VORTEX_VLOG_SOURCES)
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@for file in $(VORTEX_VLOG_SOURCES); do \
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filename=$$(basename "$$file"); \
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if [ -f $(GEN_COLLATERAL_DIR)/$$filename ]; then \
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if ! diff $$file $(GEN_COLLATERAL_DIR)/$$filename &>/dev/null ; then \
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cp -v "$$file" $(GEN_COLLATERAL_DIR); \
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fi; \
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fi; \
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done
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touch $@
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