Hansung Kim 13b9577723 Instantiate fake tensor modules outside of diplomacy
Adding them to the Diplomacy graph will cause to widen source widths
which can have area implications.

This gets rid of the need to do addResource() calls to the manually
generated Verilog files.  Their module parameters should be kept the
same as what's used in the parent Verilog module, however.
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Description
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1.2 MiB
Languages
Scala 91.6%
C++ 3.9%
Verilog 3.6%
Makefile 0.9%