Hansung Kim 759b96bcef Define ICACHE_DISABLE/DCACHE_DISABLE to keep with upstream merge
Upstream got a change that defines L1_ENABLE when {I,D}CACHE_ENABLE is
defined, which they are by default.  It also define-gates some of the
ibuffer code with L1_ENABLE which breaks the sim.  Explicitly defining
these flags prevent this from happening.
2024-03-07 16:01:42 -08:00
2024-01-30 18:01:19 -08:00
2024-01-19 16:09:41 -08:00
2024-01-17 16:40:13 -08:00
2023-03-27 14:38:02 -07:00
2024-01-17 16:40:13 -08:00
2024-01-17 16:40:13 -08:00
2024-01-17 16:40:13 -08:00
Description
No description provided
1.2 MiB
Languages
Scala 91.6%
C++ 3.9%
Verilog 3.6%
Makefile 0.9%