Fixed incorrect valid and'ing in execute
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@@ -115,7 +115,7 @@ module VX_execute_unit (
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// Actual Writeback
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assign VX_inst_exec_wb.rd = VX_exec_unit_req.rd;
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assign VX_inst_exec_wb.wb = VX_exec_unit_req.wb;
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assign VX_inst_exec_wb.wb_valid = VX_exec_unit_req.valid && !internal_stall;
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assign VX_inst_exec_wb.wb_valid = VX_exec_unit_req.valid & {`NT{!internal_stall}};
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assign VX_inst_exec_wb.wb_warp_num = VX_exec_unit_req.warp_num;
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assign VX_inst_exec_wb.alu_result = VX_exec_unit_req.jal ? duplicate_PC_data : alu_result;
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@@ -50,9 +50,9 @@ module VX_scheduler (
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wire rename_valid = rs1_rename_qual || rs2_rename_qual || rd_rename_qual;
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assign schedule_delay = ((rename_valid) && (|VX_bckE_req.valid))
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|| (memory_delay && is_mem)
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|| (gpr_stage_delay && (is_mem || is_exec))
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|| (exec_delay && is_exec);
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|| (memory_delay && is_mem)
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|| (gpr_stage_delay && (is_mem || is_exec))
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|| (exec_delay && is_exec);
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integer i;
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integer w;
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