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minor update

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This commit is contained in:
Blaise Tine
2020-09-01 00:56:10 -07:00
parent 4e8b9fb296
commit 0a45a8beb3
11 changed files with 34 additions and 21 deletions
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2
hw/opae/README
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@@ -62,7 +62,7 @@ make ase
# tests
./run_ase.sh build_ase_1c ../../driver/tests/basic/basic -n 256
./run_ase.sh build_ase_1c ../../driver/tests/demo/demo -n 16
./run_ase.sh build_ase_1c ../../driver/tests/dogfood/dogfood -n 16
./run_ase.sh build_ase_1c ../../driver/tests/dogfood/dogfood -n 1 -s4 -e4
./run_ase.sh build_ase_1c ../../benchmarks/opencl/vecadd/vecadd
# modify "vsim_run.tcl" to dump VCD trace

2
hw/opae/sources_1c.txt
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@@ -2,6 +2,8 @@
#+define+SCOPE
+define+SYNTHESIS
+define+QUARTUS
+define+FPU_FAST
#+define+DBG_PRINT_CORE_ICACHE
#+define+DBG_PRINT_CORE_DCACHE

3
hw/opae/sources_2c.txt
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@@ -1,5 +1,8 @@
+define+NUM_CORES=2
+define+L2_ENABLE=0
+define+SYNTHESIS
+define+QUARTUS
+define+FPU_FAST
vortex_afu.json
QI:vortex_afu.qsf

3
hw/opae/sources_4c.txt
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@@ -1,5 +1,8 @@
+define+NUM_CORES=4
+define+L2_ENABLE=0
+define+SYNTHESIS
+define+QUARTUS
+define+FPU_FAST
vortex_afu.json
QI:vortex_afu.qsf

3
hw/opae/vortex_afu.qsf
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@@ -5,4 +5,5 @@ set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
set_global_assignment -name VERILOG_MACRO QUARTUS
set_global_assignment -name VERILOG_MACRO SYNTHESIS
set_global_assignment -name VERILOG_MACRO NDEBUG
set_global_assignment -name MESSAGE_DISABLE 16818
set_global_assignment -name MESSAGE_DISABLE 16818
set_global_assignment -name VERILOG_MACRO FPU_FAST

4
hw/rtl/VX_config.vh
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@@ -59,10 +59,6 @@
`define EXT_F_ENABLE
`endif
`ifndef FPNEW_DISABLE
`define FPNEW_ENABLE
`endif
// Device identification
`define VENDOR_ID 0
`define ARCHITECTURE_ID 0

2
hw/rtl/VX_fpu_unit.v
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@@ -56,7 +56,7 @@ module VX_fpu_unit #(
// can accept new request?
assign fpu_req_if.ready = ready_in && ~fpuq_full;
`ifndef FPNEW_ENABLE
`ifdef FPU_FAST
VX_fp_fpga #(
.TAGW (FPUQ_BITS)

18
hw/rtl/VX_gpr_fp_ctrl.v
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@@ -23,7 +23,11 @@ module VX_gpr_fp_ctrl (
always @(posedge clk) begin
if (reset) begin
read_rs1 <= 1;
rs1_tmp_data <= 0;
rs2_tmp_data <= 0;
rs3_tmp_data <= 0;
read_rs1 <= 1;
rs3_wid <= 0;
end else begin
if (rs3_delay) begin
read_rs1 <= 0;
@@ -32,16 +36,18 @@ module VX_gpr_fp_ctrl (
read_rs1 <= 1;
end
if (read_rs1) begin
rs1_tmp_data <= rs1_data;
end
rs2_tmp_data <= rs2_data;
rs3_tmp_data <= rs1_data;
assert(read_rs1 || rs3_wid == gpr_read_if.wid);
end
end
always @(posedge clk) begin
if (read_rs1) begin
rs1_tmp_data <= rs1_data;
end
rs2_tmp_data <= rs2_data;
rs3_tmp_data <= rs1_data;
end
// outputs

14
hw/rtl/fp_cores/VX_fp_madd.v
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@@ -51,9 +51,9 @@ module VX_fp_madd #(
.chainin_invalid(),
.chainin_underflow(),
.chainin_inexact(),
.ax(),
.ax(dataa[i]),
.ay(datab[i]),
.az(dataa[i]),
.az(),
.clk({2'b00,clk}),
.ena({2'b11,~stall}),
.aclr(2'b00),
@@ -75,12 +75,12 @@ module VX_fp_madd #(
defparam mac_fp_add.adder_subtract = "false";
defparam mac_fp_add.ax_clock = "0";
defparam mac_fp_add.ay_clock = "0";
defparam mac_fp_add.az_clock = "0";
defparam mac_fp_add.az_clock = "none";
defparam mac_fp_add.output_clock = "0";
defparam mac_fp_add.accumulate_clock = "none";
defparam mac_fp_add.ax_chainin_pl_clock = "0";
defparam mac_fp_add.ax_chainin_pl_clock = "none";
defparam mac_fp_add.accum_pipeline_clock = "none";
defparam mac_fp_add.mult_pipeline_clock = "0";
defparam mac_fp_add.mult_pipeline_clock = "none";
defparam mac_fp_add.adder_input_clock = "0";
defparam mac_fp_add.accum_adder_clock = "none";
@@ -91,9 +91,9 @@ module VX_fp_madd #(
.chainin_invalid(),
.chainin_underflow(),
.chainin_inexact(),
.ax(),
.ax(dataa[i]),
.ay(datab[i]),
.az(dataa[i]),
.az(),
.clk({2'b00,clk}),
.ena({2'b11,~stall}),
.aclr(2'b00),

2
hw/rtl/fp_cores/VX_fp_nmadd.v
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@@ -52,7 +52,7 @@ module VX_fp_nmadd #(
.ay(datab[i]),
.az(dataa[i]),
.clk({2'b00,clk}),
.ena({2'b11,~stall),
.ena({2'b11,~stall}),
.aclr(2'b00),
.chainin(),
// outputs

2
hw/syn/quartus/project.tcl
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@@ -38,6 +38,8 @@ set_global_assignment -name VERILOG_MACRO QUARTUS
set_global_assignment -name VERILOG_MACRO SYNTHESIS
set_global_assignment -name VERILOG_MACRO NDEBUG
set_global_assignment -name MESSAGE_DISABLE 16818
set_global_assignment -name VERILOG_MACRO FPU_FAST
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"