verilator suppor for opae (partial)

Makefile

@@ -0,0 +1,5 @@
+all:
+   $(MAKE) -C hw
+   $(MAKE) -C driver
+   $(MAKE) -C runtime
+   $(MAKE) -C simX

driver/common/vx_utils.cpp

@@ -2,7 +2,7 @@
 #include <fstream>
 #include <cstring>
 #include <vortex.h>
-#include <config.h>
+#include <VX_config.h>
 
 extern int vx_dev_caps(int caps_id) {
   switch (caps_id) {

driver/opae/Makefile

@@ -1,7 +1,7 @@
 
 CXXFLAGS += -std=c++11 -O0 -g -Wall -Wextra -pedantic -Wfatal-errors
 
-CXXFLAGS += -I../include -I/tools/opae/1.4.0/include  -I../../runtime
+CXXFLAGS += -I../include -I/tools/opae/1.4.0/include  -I../../hw
 
 LDFLAGS += -L/tools/opae/1.4.0/lib
 

driver/rtlsim/Makefile

@@ -19,6 +19,7 @@ DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \
 MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2
 
 #DEBUG = 1
+AFU=1
 
 CFLAGS += -fPIC
 
@@ -27,6 +28,8 @@ CFLAGS += -DUSE_RTLSIM $(MULTICORE)
 LDFLAGS += -shared -pthread
 # LDFLAGS += -dynamiclib -pthread
 
+TOP = Vortex_Socket
+
 SRCS = vortex.cpp ../common/vx_utils.cpp ../../hw/simulate/simulator.cpp
 
 RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/libs -I../../hw/rtl/interfaces -I../../hw/rtl/pipe_regs -I../../hw/rtl/cache
@@ -48,14 +51,22 @@ else
 	VL_FLAGS += -DNDEBUG
 endif
 
+# AFU
+ifdef AFU
+    TOP = vortex_afu_sim
+	VL_FLAGS += -DNOPAE
+	CFLAGS += -DNOPAE
+	RTL_INCLUDE += -I../../hw/opae  -I../../hw/opae/ccip
+endif
+
 PROJECT = libvortex.so
 # PROJECT = libvortex.dylib
 
 all: $(PROJECT)
 	
 $(PROJECT): $(SRCS)
-	verilator --exe --cc Vortex_Socket.v $(RTL_INCLUDE) $(VL_FLAGS) $(SRCS) -CFLAGS '$(CFLAGS)' -LDFLAGS '$(LDFLAGS)' -o ../$(PROJECT)
+	verilator --exe --cc $(TOP) $(RTL_INCLUDE) $(VL_FLAGS) $(SRCS) -CFLAGS '$(CFLAGS)' -LDFLAGS '$(LDFLAGS)' -o ../$(PROJECT)
-	make -j -C obj_dir -f VVortex_Socket.mk
+	make -j -C obj_dir -f V$(TOP).mk
 
 clean:
 	rm -rf $(PROJECT) obj_dir

driver/rtlsim/ram.h

@@ -0,0 +1,64 @@
+#pragma once
+
+#include <stdio.h>
+#include <stdint.h>
+
+class RAM {
+private:
+
+  mutable uint8_t *mem_[(1 << 12)];      
+
+  uint8_t *get(uint32_t address) const {
+    uint32_t block_addr   = address >> 20;
+    uint32_t block_offset = address & 0x000FFFFF;
+    if (mem_[block_addr] == NULL) {
+      mem_[block_addr] = new uint8_t[(1 << 20)];
+    }
+    return mem_[block_addr] + block_offset;
+  }
+
+public:
+
+  RAM() {
+    for (uint32_t i = 0; i < (1 << 12); i++) {
+      mem_[i] = NULL;
+    }
+  }
+
+  ~RAM() {
+    this->clear();
+  }
+
+  size_t size() const {
+    return (1ull << 32);
+  }
+
+  void clear() {
+    for (uint32_t i = 0; i < (1 << 12); i++) {
+      if (mem_[i]) {
+        delete mem_[i];
+        mem_[i] = NULL;
+      }
+    }
+  }
+
+  void read(uint32_t address, uint32_t length, uint8_t *data) const {
+    for (unsigned i = 0; i < length; i++) {
+      data[i] = *this->get(address + i);
+    }
+  }
+
+  void write(uint32_t address, uint32_t length, const uint8_t *data) {
+    for (unsigned i = 0; i < length; i++) {
+      *this->get(address + i) = data[i];
+    }
+  }
+
+  uint8_t& operator[](uint32_t address) {
+    return *get(address);
+  }
+
+  const uint8_t& operator[](uint32_t address) const {
+    return *get(address);
+  }
+};

driver/rtlsim/simulator.cpp

@@ -0,0 +1,70 @@
+#include "simulator.h"
+#include <iostream>
+#include <fstream>
+#include <iomanip>
+
+uint64_t timestamp = 0;
+
+double sc_time_stamp() { 
+  return timestamp;
+}
+
+Simulator::Simulator() {    
+  // force random values for unitialized signals
+  const char* args[] = {"", "+verilator+rand+reset+2", "+verilator+seed+50"};
+  Verilated::commandArgs(3, args);
+
+  vortex_ = new Vvortex_afu_sim();
+
+#ifdef VCD_OUTPUT
+  Verilated::traceEverOn(true);
+  trace_ = new VerilatedVcdC;
+  vortex_->trace(trace_, 99);
+  trace_->open("trace.vcd");
+#endif  
+}
+
+Simulator::~Simulator() {
+#ifdef VCD_OUTPUT
+  trace_->close();
+#endif
+  delete vortex_;
+}
+
+void Simulator::reset() {     
+#ifndef NDEBUG
+  std::cout << timestamp << ": [sim] reset()" << std::endl;
+#endif 
+  vortex_->reset = 1;
+  this->step();  
+  vortex_->reset = 0;
+
+  dram_rsp_vec_.clear();
+}
+
+void Simulator::step() {
+  vortex_->clk = 0;
+  this->eval();
+
+  vortex_->clk = 1;
+  this->eval();
+
+  avs_driver();
+  ccip_driver();
+}
+
+void Simulator::eval() {
+  vortex_->eval();
+#ifdef VCD_OUTPUT
+  trace_->dump(timestamp);
+#endif
+  ++timestamp;
+}
+
+void Simulator::avs_driver() {
+  //--
+}
+
+ void Simulator::ccip_driver() {
+   //--
+ }

driver/rtlsim/simulator.h

@@ -0,0 +1,59 @@
+#pragma once
+
+#include "Vvortex_afu_sim.h"
+#include "Vvortex_afu_sim__Syms.h"
+#include "verilated.h"
+
+#ifdef VCD_OUTPUT
+#include <verilated_vcd_c.h>
+#endif
+
+#include <VX_config.h>
+#include "ram.h"
+
+#include <ostream>
+#include <vector>
+
+#define ENABLE_DRAM_STALLS
+#define DRAM_LATENCY 100
+#define DRAM_RQ_SIZE 16
+#define DRAM_STALLS_MODULO 16
+
+typedef struct {
+  int cycles_left;  
+  uint8_t *data;
+  unsigned tag;
+} dram_req_t;
+
+class Simulator {
+public:
+  
+  Simulator();
+  virtual ~Simulator();
+
+  void reset();
+  
+  void step();  
+
+  int mmio_read(uint64_t addr, uint64_t* value);
+
+  int mmio_write(uint64_t addr, uint64_t value);
+  
+private:  
+
+  void eval(); 
+
+  void avs_driver();
+
+  void ccip_driver(); 
+  
+  std::vector<dram_req_t> dram_rsp_vec_;
+
+  RAM ram_;
+  Vvortex_afu_sim *vortex_;
+  
+
+#ifdef VCD_OUTPUT
+  VerilatedVcdC *trace_;
+#endif
+};

driver/rtlsim/vortex.cpp

@@ -7,7 +7,6 @@
 #include <chrono>
 
 #include <vortex.h>
-#include <ram.h>
 #include <simulator.h>
 
 ///////////////////////////////////////////////////////////////////////////////
@@ -60,7 +59,6 @@ class vx_device {
 public:
     vx_device() {        
         mem_allocation_ = vx_dev_caps(VX_CAPS_ALLOC_BASE_ADDR);
-        simulator_.attach_ram(&ram_);
     } 
 
     ~vx_device() {     
@@ -146,7 +144,6 @@ public:
 private:
 
     size_t mem_allocation_;     
-    RAM ram_;
     Simulator simulator_;
     std::future<void> future_;
 };

driver/simx/Makefile

@@ -1,7 +1,7 @@
 CFLAGS += -std=c++11 -O3 -Wall -Wextra -pedantic -Wfatal-errors
 #CFLAGS += -std=c++11 -g -O0 -Wall -Wextra -pedantic -Wfatal-errors
 
-CFLAGS += -I../../include -I../../../simX/include -I../../../runtime
+CFLAGS += -I../../include -I../../../simX/include -I../../../hw
 
 CFLAGS += -fPIC
 

driver/simx/vortex.cpp

@@ -9,7 +9,7 @@
 
 #include <vortex.h>
 #include <core.h>
-#include <config.h>
+#include <VX_config.h>
 
 #define PAGE_SIZE 4096
 

driver/tests/basic/Makefile

@@ -15,6 +15,7 @@ VX_API = $(VX_RT_PATH)/vx_api/vx_api.c
 VX_FIO = $(VX_RT_PATH)/fileio/fileio.S
 
 VX_CFLAGS = -march=rv32im -mabi=ilp32 -O3 -Wl,-Bstatic,-T,$(VX_RT_PATH)/startup/vx_link.ld -ffreestanding -nostartfiles -Wl,--gc-sections
+VX_CFLAGS += -I../../../hw 
 
 VX_SRCS = kernel.c
 

driver/tests/basic/common.h

@@ -1,8 +1,8 @@
 #ifndef _COMMON_H_
 #define _COMMON_H_
 
-#define DEV_MEM_SRC_ADDR 0x10000000
+#define DEV_MEM_SRC_ADDR 0x10000040
-#define DEV_MEM_DST_ADDR 0x20000000
+#define DEV_MEM_DST_ADDR 0x20000080
 #define NUM_BLOCKS       64
 
 #endif

driver/tests/basic/kernel.c

@@ -1,5 +1,5 @@
 #include <stdint.h>
-#include "config.h"
+#include <VX_config.h>
 #include "intrinsics/vx_intrinsics.h"
 #include "common.h"
 

driver/tests/demo/Makefile

@@ -14,6 +14,7 @@ VX_API = $(VX_RT_PATH)/vx_api/vx_api.c
 #VX_FIO = $(VX_RT_PATH)/fileio/fileio.S
 
 VX_CFLAGS = -march=rv32im -mabi=ilp32 -O3 -Wl,-Bstatic,-T,$(VX_RT_PATH)/startup/vx_link.ld -ffreestanding -nostartfiles -Wl,--gc-sections
+VX_CFLAGS += -I../../../hw 
 
 VX_SRCS = kernel.c
 

hw/Makefile

@@ -1,95 +1,4 @@
-all: build-s
-
-CF += -std=c++11 -fms-extensions
-
-VF += --language 1800-2009 --assert -Wall -Wpedantic
-VF += -Wno-DECLFILENAME
-VF += --x-initial unique
-
-VF += -exe $(SRCS) $(INCLUDE)
-
-#MULTICORE += -DNUM_CLUSTERS=2 -DNUM_CORES=4
-#MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=4
-MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2
-
-# control RTL debug print states
-DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \
-				  -DDBG_PRINT_CORE_DCACHE \
-			      -DDBG_PRINT_CACHE_BANK  \
-				  -DDBG_PRINT_CACHE_SNP   \
-				  -DDBG_PRINT_CACHE_MSRQ  \
-				  -DDBG_PRINT_DRAM        \
-				  -DDBG_PRINT_OPAE
-
-#DBG_PRINT=$(DBG_PRINT_FLAGS)
-
-INCLUDE = -I./rtl/ -I./rtl/libs -I./rtl/interfaces -I./rtl/pipe_regs -I./rtl/cache -I./rtl/simulate
-
-SRCS += ./simulate/testbench.cpp ./simulate/simulator.cpp
-
-DBG += -DVCD_OUTPUT $(DBG_PRINT)
-
-THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')
-
 .PHONY: build_config
 
 build_config:
-	./scripts/gen_config.py --outv ./rtl/VX_user_config.vh --outc ./simulate/VX_config.h
+	./scripts/gen_config.py --outv ./rtl/VX_user_config.vh --outc ./VX_config.h
-
-gen-s: build_config
-	verilator $(VF) -DNDEBUG -cc Vortex_Socket.v -CFLAGS '$(CF) -DNDEBUG'
-
-gen-sd: build_config
-	verilator $(VF) -cc Vortex_Socket.v -CFLAGS '$(CF) -g -O0  $(DBG)' --trace $(DBG)
-
-gen-st: build_config
-	verilator $(VF) -DNDEBUG -cc Vortex_Socket.v -CFLAGS '$(CF) -DNDEBUG -O2' --threads $(THREADS)
-
-gen-m: build_config
-	verilator $(VF) -DNDEBUG -cc Vortex_Socket.v $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG $(MULTICORE)'
-	
-gen-md: build_config
-	verilator $(VF) -cc Vortex_Socket.v $(MULTICORE) -CFLAGS '$(CF) -g -O0 $(DBG) $(MULTICORE)' --trace $(DBG)
-
-gen-mt: build_config
-	verilator $(VF) -DNDEBUG -cc Vortex_Socket.v $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG -O2 $(MULTICORE)' --threads $(THREADS)
-
-build-s: gen-s
-	(cd obj_dir && make -j -f VVortex_Socket.mk)
-
-build-sd: gen-sd
-	(cd obj_dir && make -j -f VVortex_Socket.mk)
-
-build-st: gen-st
-	(cd obj_dir && make -j -f VVortex_Socket.mk)
-
-build-m: gen-m
-	(cd obj_dir && make -j -f VVortex_Socket.mk)
-
-build-md: gen-md
-	(cd obj_dir && make -j -f VVortex_Socket.mk)
-
-build-mt: gen-mt
-	(cd obj_dir && make -j -f VVortex_Socket.mk)
-
-run: run-s
-run-s: build-s
-	(cd obj_dir && ./VVortex_Socket)
-
-run-sd: build-sd
-	(cd obj_dir && ./VVortex_Socket)
-
-run-st: build-st
-	(cd obj_dir && ./VVortex_Socket)
-
-run-m: build-m
-	(cd obj_dir && ./VVortex_Socket)
-
-run-md: build-md
-	(cd obj_dir && ./VVortex_Socket)
-
-run-mt: build-mt
-	(cd obj_dir && ./VVortex_Socket)
-
-clean:
-	rm -rf obj_dir

hw/opae/ccip/ccip_if_pkg.sv

@@ -0,0 +1,238 @@
+// Date: 02/2/2016
+// Compliant with CCI-P spec v0.71
+package ccip_if_pkg;
+
+//=====================================================================
+// CCI-P interface defines
+//=====================================================================
+parameter CCIP_VERSION_NUMBER    = 12'h071;
+
+parameter CCIP_CLADDR_WIDTH      = 42; 
+parameter CCIP_CLDATA_WIDTH      = 512; 
+
+parameter CCIP_MMIOADDR_WIDTH    = 16; 
+parameter CCIP_MMIODATA_WIDTH    = 64; 
+parameter CCIP_TID_WIDTH         = 9; 
+
+parameter CCIP_MDATA_WIDTH       = 16; 
+
+
+// Number of requests that can be accepted after almost full is asserted. 
+parameter CCIP_TX_ALMOST_FULL_THRESHOLD = 8; 
+
+parameter CCIP_MMIO_RD_TIMEOUT = 512;
+
+parameter CCIP_SYNC_RESET_POLARITY=1;       // Active High Reset
+
+// Base types 
+//---------------------------------------------------------------------- 
+typedef logic [CCIP_CLADDR_WIDTH-1:0]   t_ccip_clAddr;
+typedef logic [CCIP_CLDATA_WIDTH-1:0]   t_ccip_clData;
+
+
+typedef logic [CCIP_MMIOADDR_WIDTH-1:0] t_ccip_mmioAddr;
+typedef logic [CCIP_MMIODATA_WIDTH-1:0] t_ccip_mmioData;
+typedef logic [CCIP_TID_WIDTH-1:0]      t_ccip_tid;
+
+
+typedef logic [CCIP_MDATA_WIDTH-1:0]    t_ccip_mdata;
+typedef logic [1:0]                     t_ccip_clNum;
+typedef logic [2:0]                     t_ccip_qwIdx;
+
+  
+// Request Type  Encodings
+//----------------------------------------------------------------------
+// Channel 0
+typedef enum logic [3:0] {
+    eREQ_RDLINE_I  = 4'h0,      // Memory Read with FPGA Cache Hint=Invalid
+    eREQ_RDLINE_S  = 4'h1       // Memory Read with FPGA Cache Hint=Shared
+} t_ccip_c0_req;
+
+// Channel 1
+typedef enum logic [3:0] {
+    eREQ_WRLINE_I  = 4'h0,      // Memory Write with FPGA Cache Hint=Invalid
+    eREQ_WRLINE_M  = 4'h1,      // Memory Write with FPGA Cache Hint=Modified
+    eREQ_WRPUSH_I  = 4'h2,      // Memory Write with DDIO Hint ** NOT SUPPORTED CURRENTLY **
+    eREQ_WRFENCE   = 4'h4,      // Memory Write Fence
+//    eREQ_ATOMIC    = 4'h5,      // Atomic operation: Compare-Exchange for Memory Addr  ** NOT SUPPORTED CURRENTELY **
+    eREQ_INTR      = 4'h6       // Interrupt the CPU ** NOT SUPPORTED CURRENTLY **
+} t_ccip_c1_req;
+
+// Response Type  Encodings
+//----------------------------------------------------------------------
+// Channel 0
+typedef enum logic [3:0] {
+    eRSP_RDLINE     = 4'h0,     // Memory Read
+    eRSP_UMSG       = 4'h4      // UMsg received
+//    eRSP_ATOMIC     = 4'h5      // Atomic Operation: Compare-Exchange for Memory Addr
+} t_ccip_c0_rsp;
+
+// Channel 1
+typedef enum logic [3:0] {
+    eRSP_WRLINE     = 4'h0,     // Memory Write
+    eRSP_WRFENCE    = 4'h4,     // Memory Write Fence 
+    eRSP_INTR       = 4'h6      // Interrupt delivered to the CPU ** NOT SUPPORTED CURRENTLY **
+} t_ccip_c1_rsp;
+
+//
+// Virtual Channel Select
+//----------------------------------------------------------------------
+typedef enum logic [1:0] {
+    eVC_VA  = 2'b00,
+    eVC_VL0 = 2'b01,
+    eVC_VH0 = 2'b10,
+    eVC_VH1 = 2'b11
+} t_ccip_vc;
+
+// Multi-CL Memory Request
+//----------------------------------------------------------------------
+typedef enum logic [1:0] {
+    eCL_LEN_1 = 2'b00,
+    eCL_LEN_2 = 2'b01,
+    eCL_LEN_4 = 2'b11
+} t_ccip_clLen;
+
+//
+// Structures for Request and Response headers
+//----------------------------------------------------------------------
+typedef struct packed {
+    t_ccip_vc       vc_sel;
+    logic [1:0]     rsvd1;     // reserved, drive 0
+    t_ccip_clLen    cl_len;
+    t_ccip_c0_req   req_type;
+    logic [5:0]     rsvd0;     // reserved, drive 0
+    t_ccip_clAddr   address;
+    t_ccip_mdata    mdata;
+} t_ccip_c0_ReqMemHdr;
+parameter CCIP_C0TX_HDR_WIDTH = $bits(t_ccip_c0_ReqMemHdr);
+
+typedef struct packed {
+    logic [5:0]     rsvd2;
+    t_ccip_vc       vc_sel;
+    logic           sop;
+    logic           rsvd1;     // reserved, drive 0
+    t_ccip_clLen    cl_len;
+    t_ccip_c1_req   req_type;
+    logic [5:0]     rsvd0;     // reserved, drive 0
+    t_ccip_clAddr   address;
+    t_ccip_mdata    mdata;
+} t_ccip_c1_ReqMemHdr;
+parameter CCIP_C1TX_HDR_WIDTH = $bits(t_ccip_c1_ReqMemHdr);
+
+typedef struct packed {
+    logic [5:0]     rsvd2;          // reserved, drive 0
+    t_ccip_vc       vc_sel;
+    logic [3:0]     rsvd1;          // reserved, drive 0
+    t_ccip_c1_req   req_type;
+    logic [47:0]    rsvd0;          // reserved, drive 0
+    t_ccip_mdata    mdata;
+}t_ccip_c1_ReqFenceHdr;
+
+typedef struct packed {
+    t_ccip_vc       vc_used;
+    logic           rsvd1;          // reserved, don't care
+    logic           hit_miss;
+    logic [1:0]     rsvd0;          // reserved, don't care
+    t_ccip_clNum    cl_num;
+    t_ccip_c0_rsp   resp_type;
+    t_ccip_mdata    mdata;
+} t_ccip_c0_RspMemHdr;
+parameter CCIP_C0RX_HDR_WIDTH = $bits(t_ccip_c0_RspMemHdr);
+
+typedef struct packed {
+    t_ccip_vc       vc_used;
+    logic           rsvd1;          // reserved, don't care
+    logic           hit_miss;
+    logic           format;
+    logic           rsvd0;          // reserved, don't care
+    t_ccip_clNum    cl_num;
+    t_ccip_c1_rsp   resp_type;
+    t_ccip_mdata    mdata;
+} t_ccip_c1_RspMemHdr;
+parameter CCIP_C1RX_HDR_WIDTH = $bits(t_ccip_c1_RspMemHdr);
+
+typedef struct packed {
+    logic [7:0]     rsvd0;          // reserved, don't care
+    t_ccip_c1_rsp   resp_type;
+    t_ccip_mdata    mdata;
+} t_ccip_c1_RspFenceHdr;
+
+// Alternate Channel 0 MMIO request from host : 
+//  MMIO requests arrive on the same channel as read responses, sharing
+//  t_if_ccip_c0_Rx below.  When either mmioRdValid or mmioWrValid is set
+//  the message is an MMIO request and should be processed by casting
+//  t_if_ccip_c0_Rx.hdr to t_ccip_c0_ReqMmioHdr.
+typedef struct packed {
+    t_ccip_mmioAddr address;    // 4B aligned Mmio address
+    logic [1:0]     length;     // 2'b00- 4B, 2'b01- 8B, 2'b10- 64B
+    logic           rsvd;       // reserved, don't care
+    t_ccip_tid      tid;
+} t_ccip_c0_ReqMmioHdr;
+
+typedef struct packed {
+    t_ccip_tid     tid;         // Returned back from ReqMmioHdr
+} t_ccip_c2_RspMmioHdr;
+parameter CCIP_C2TX_HDR_WIDTH = $bits(t_ccip_c2_RspMmioHdr);
+
+//------------------------------------------------------------------------
+// CCI-P Input & Output bus structures 
+// 
+// Users are encouraged to use these for AFU development
+//------------------------------------------------------------------------
+// Channel 0 : Memory Reads
+typedef struct packed { 
+    t_ccip_c0_ReqMemHdr  hdr;            // Request Header 
+    logic                valid;          // Request Valid 
+} t_if_ccip_c0_Tx; 
+
+
+// Channel 1 : Memory Writes,  Interrupts, CmpXchg
+typedef struct packed { 
+    t_ccip_c1_ReqMemHdr  hdr;            // Request Header 
+    t_ccip_clData        data;           // Request Data 
+    logic                valid;          // Request Wr Valid 
+} t_if_ccip_c1_Tx; 
+
+// Channel 2 : MMIO Read response
+typedef struct packed { 
+    t_ccip_c2_RspMmioHdr    hdr;            // Response Header 
+    logic                   mmioRdValid;    // Response Read Valid 
+    t_ccip_mmioData         data;           // Response Data 
+} t_if_ccip_c2_Tx; 
+  
+// Wrap all Tx channels
+typedef struct packed {
+    t_if_ccip_c0_Tx      c0; 
+    t_if_ccip_c1_Tx      c1; 
+    t_if_ccip_c2_Tx      c2; 
+} t_if_ccip_Tx;
+
+// Channel 0: Memory Read response, MMIO Request
+typedef struct packed { 
+    t_ccip_c0_RspMemHdr  hdr;            //  Rd Response/ MMIO req Header
+    t_ccip_clData        data;           //  Rd Data / MMIO req Data 
+    // Only one of valid, mmioRdValid and mmioWrValid may be set
+    // in a cycle.  When either mmioRdValid or mmioWrValid are true
+    // the hdr must be processed specially.  See t_ccip_c0_ReqMmioHdr
+    // above.
+    logic                rspValid;       //  Rd Response Valid 
+    logic                mmioRdValid;    //  MMIO Read Valid
+    logic                mmioWrValid;    //  MMIO Write Valid
+} t_if_ccip_c0_Rx;
+
+// Channel 1: Memory Writes 
+typedef struct packed { 
+    t_ccip_c1_RspMemHdr  hdr;            //  Response Header 
+    logic                rspValid;       //  Response Valid 
+} t_if_ccip_c1_Rx; 
+
+// Wrap all channels 
+typedef struct packed { 
+    logic                c0TxAlmFull;    //  C0 Request Channel Almost Full 
+    logic                c1TxAlmFull;    //  C1 Request Channel Almost Full 
+
+    t_if_ccip_c0_Rx      c0; 
+    t_if_ccip_c1_Rx      c1; 
+} t_if_ccip_Rx;
+
+endpackage

hw/opae/ccip/local_mem_cfg_pkg.sv

@@ -0,0 +1,61 @@
+//
+// Copyright (c) 2017, Intel Corporation
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice, this
+// list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// Neither the name of the Intel Corporation nor the names of its contributors
+// may be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+
+//`include "platform_afu_top_config.vh"
+
+`ifdef PLATFORM_PROVIDES_LOCAL_MEMORY
+
+package local_mem_cfg_pkg;
+
+    parameter LOCAL_MEM_VERSION_NUMBER = 1;
+
+    parameter LOCAL_MEM_ADDR_WIDTH = `PLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH;
+    parameter LOCAL_MEM_DATA_WIDTH = `PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH;
+
+    parameter LOCAL_MEM_BURST_CNT_WIDTH = `PLATFORM_PARAM_LOCAL_MEMORY_BURST_CNT_WIDTH;
+
+    // Number of bytes in a data line
+    parameter LOCAL_MEM_DATA_N_BYTES = LOCAL_MEM_DATA_WIDTH / 8;
+
+
+    // Base types
+    // --------------------------------------------------------------------
+
+    typedef logic [LOCAL_MEM_ADDR_WIDTH-1:0] t_local_mem_addr;
+    typedef logic [LOCAL_MEM_DATA_WIDTH-1:0] t_local_mem_data;
+
+    typedef logic [LOCAL_MEM_BURST_CNT_WIDTH-1:0] t_local_mem_burst_cnt;
+
+    // Byte-level mask of a data line
+    typedef logic [LOCAL_MEM_DATA_N_BYTES-1:0] t_local_mem_byte_mask;
+
+endpackage // local_mem_cfg_pkg
+
+`endif // PLATFORM_PROVIDES_LOCAL_MEMORY

hw/rtl/VX_dram_arb.v

@@ -1,4 +1,4 @@
-`include "VX_cache_config.vh"
+`include "VX_define.vh"
 
 module VX_dram_arb #(
     parameter BANK_LINE_SIZE = 1, 

hw/rtl/Vortex.v

@@ -1,5 +1,4 @@
 `include "VX_define.vh"
-`include "VX_cache_config.vh"
 
 module Vortex #( 
     parameter CORE_ID = 0

hw/rtl/Vortex_Cluster.v

@@ -1,5 +1,4 @@
 `include "VX_define.vh"
-`include "VX_cache_config.vh"
 
 module Vortex_Cluster #(
     parameter CLUSTER_ID = 0

hw/rtl/Vortex_Socket.v

@@ -1,5 +1,4 @@
 `include "VX_define.vh"
-`include "VX_cache_config.vh"
 
 module Vortex_Socket (
     // Clock

hw/rtl/libs/VX_generic_queue.v

@@ -132,7 +132,7 @@ module VX_generic_queue #(
                             wr_ptr_r <= wr_ptr_r + 1; 
                             if (!reading) begin                                
                                 empty_r <= 0;
-                                if (size_r == SIZE-1) begin
+                                if (size_r == $bits(size_r)'(SIZE-1)) begin
                                     full_r <= 1;
                                 end
                                 size_r <= size_r + 1;

hw/simulate/Makefile

@@ -0,0 +1,89 @@
+#MULTICORE += -DNUM_CLUSTERS=2 -DNUM_CORES=4
+#MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=4
+MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2
+
+# control RTL debug print states
+DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \
+				  -DDBG_PRINT_CORE_DCACHE \
+			      -DDBG_PRINT_CACHE_BANK  \
+				  -DDBG_PRINT_CACHE_SNP   \
+				  -DDBG_PRINT_CACHE_MSRQ  \
+				  -DDBG_PRINT_DRAM        \
+				  -DDBG_PRINT_OPAE
+
+#DBG_PRINT=$(DBG_PRINT_FLAGS)
+
+INCLUDE = -I../rtl/ -I../rtl/libs -I../rtl/interfaces -I../rtl/pipe_regs -I../rtl/cache -I../rtl/simulate
+
+SRCS = simulator.cpp testbench.cpp
+
+all: build-s
+
+CF += -std=c++11 -fms-extensions -I../..
+
+VF += --language 1800-2009 --assert -Wall -Wpedantic
+VF += -Wno-DECLFILENAME
+VF += --x-initial unique
+VF += -exe $(SRCS) $(INCLUDE)
+
+DBG += -DVCD_OUTPUT $(DBG_PRINT)
+
+THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')
+
+gen-s:
+	verilator $(VF) -DNDEBUG -cc Vortex_Socket.v -CFLAGS '$(CF) -DNDEBUG'
+
+gen-sd:
+	verilator $(VF) -cc Vortex_Socket.v -CFLAGS '$(CF) -g -O0  $(DBG)' --trace $(DBG)
+
+gen-st:
+	verilator $(VF) -DNDEBUG -cc Vortex_Socket.v -CFLAGS '$(CF) -DNDEBUG -O2' --threads $(THREADS)
+
+gen-m:
+	verilator $(VF) -DNDEBUG -cc Vortex_Socket.v $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG $(MULTICORE)'
+	
+gen-md:
+	verilator $(VF) -cc Vortex_Socket.v $(MULTICORE) -CFLAGS '$(CF) -g -O0 $(DBG) $(MULTICORE)' --trace $(DBG)
+
+gen-mt:
+	verilator $(VF) -DNDEBUG -cc Vortex_Socket.v $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG -O2 $(MULTICORE)' --threads $(THREADS)
+
+build-s: gen-s
+	(cd obj_dir && make -j -f VVortex_Socket.mk)
+
+build-sd: gen-sd
+	(cd obj_dir && make -j -f VVortex_Socket.mk)
+
+build-st: gen-st
+	(cd obj_dir && make -j -f VVortex_Socket.mk)
+
+build-m: gen-m
+	(cd obj_dir && make -j -f VVortex_Socket.mk)
+
+build-md: gen-md
+	(cd obj_dir && make -j -f VVortex_Socket.mk)
+
+build-mt: gen-mt
+	(cd obj_dir && make -j -f VVortex_Socket.mk)
+
+run: run-s
+run-s: build-s
+	(cd obj_dir && ./VVortex_Socket)
+
+run-sd: build-sd
+	(cd obj_dir && ./VVortex_Socket)
+
+run-st: build-st
+	(cd obj_dir && ./VVortex_Socket)
+
+run-m: build-m
+	(cd obj_dir && ./VVortex_Socket)
+
+run-md: build-md
+	(cd obj_dir && ./VVortex_Socket)
+
+run-mt: build-mt
+	(cd obj_dir && ./VVortex_Socket)
+
+clean:
+	rm -rf obj_dir

hw/simulate/simulator.cpp

@@ -17,14 +17,6 @@ Simulator::Simulator() {
   ram_ = nullptr;
   vortex_ = new VVortex_Socket();
 
-  // initial values
-  vortex_->dram_req_ready = 0;
-  vortex_->dram_rsp_valid = 0;
-  vortex_->io_req_ready   = 0;
-  vortex_->io_rsp_valid   = 0;
-  vortex_->snp_req_valid  = 0;
-  vortex_->snp_rsp_ready  = 0;
-
 #ifdef VCD_OUTPUT
   Verilated::traceEverOn(true);
   trace_ = new VerilatedVcdC;

hw/simulate/simulator.h

@@ -8,7 +8,7 @@
 #include <verilated_vcd_c.h>
 #endif
 
-#include "VX_config.h"
+#include <VX_config.h>
 #include "ram.h"
 
 #include <ostream>

runtime/Makefile

@@ -1,6 +1,4 @@
 
-.PHONY: build_config
+all:
-build_config:
-	../hw/scripts/gen_config.py --outv none --outc ./config.h
 
 

runtime/fileio/fileio.S

@@ -1,5 +1,4 @@
-
+#include <VX_config.h>
-#include "../config.h"
 
 # .section .FileIO
 

runtime/intrinsics/vx_intrinsics.S

@@ -1,4 +1,4 @@
-#include "../config.h"
+#include <VX_config.h>
 
 .section .text
 

runtime/io/vx_io.S

@@ -1,4 +1,4 @@
-#include "../config.h"
+#include <VX_config.h>
 
 .type vx_print_str, @function
 .global vx_print_str

runtime/startup/vx_start.S

@@ -1,4 +1,4 @@
-#include "../config.h"
+#include <VX_config.h>
 
 .section .init, "ax"
 .global _start

runtime/tests/simple/Makefile

@@ -4,6 +4,8 @@ COMP     = ~/dev/riscv-gnu-toolchain/drops/bin/riscv32-unknown-elf-g++
 CC_FLAGS = -march=rv32im -mabi=ilp32 -O3 -Wl,-Bstatic,-T,../../startup/vx_link.ld 
 CC_FLAGS += -nostartfiles -ffreestanding -fno-rtti -fno-exceptions -Wl,--gc-sections 
 
+CC_FLAGS += -I../../../hw
+
 DMP  = ~/dev/riscv-gnu-toolchain/drops/bin/riscv32-unknown-elf-objdump
 CPY  = ~/dev/riscv-gnu-toolchain/drops/bin/riscv32-unknown-elf-objcopy
 

runtime/vx_api/vx_api.c

@@ -1,4 +1,4 @@
-#include "../config.h"
+#include <VX_config.h>
 #include "../intrinsics/vx_intrinsics.h"
 #include "vx_api.h"
 #include <inttypes.h>

simX/simX.cpp

@@ -21,7 +21,7 @@
 #include "include/args.h"
 #include "include/help.h"
 
-#include "../runtime/config.h"
+#include <VX_config.h>
 
 #include <sys/stat.h>