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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-20 13:52:24 -04:00
parent 94e4f056db
commit 1a2823da0d
31 changed files with 253 additions and 260 deletions
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38
hw/rtl/VX_csr_data.v
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@@ -4,19 +4,19 @@ module VX_csr_data (
input wire clk, // Clock
input wire reset,
input wire[`CSR_ADDR_SIZE-1:0] in_read_csr_address,
input wire in_write_valid,
input wire[`CSR_WIDTH-1:0] in_write_csr_data,
input wire[`CSR_ADDR_SIZE-1:0] read_csr_address_i,
input wire write_valid_i,
input wire[`CSR_WIDTH-1:0] write_csr_data_i,
`IGNORE_WARNINGS_BEGIN
// We use a smaller storage for CSRs than the standard 4KB in RISC-V
input wire[`CSR_ADDR_SIZE-1:0] in_write_csr_address,
input wire[`CSR_ADDR_SIZE-1:0] write_csr_address_i,
`IGNORE_WARNINGS_END
output wire[31:0] out_read_csr_data,
output wire[31:0] read_csr_data_o,
// For instruction retire counting
input wire in_writeback_valid
input wire writeback_valid_i
);
// wire[`NUM_THREADS-1:0][31:0] thread_ids;
// wire[`NUM_THREADS-1:0][31:0] warp_ids;
@@ -41,21 +41,21 @@ module VX_csr_data (
wire read_instret;
wire read_instreth;
assign read_cycle = in_read_csr_address == `CSR_CYCL_L;
assign read_cycleh = in_read_csr_address == `CSR_CYCL_H;
assign read_instret = in_read_csr_address == `CSR_INST_L;
assign read_instreth = in_read_csr_address == `CSR_INST_H;
assign read_cycle = read_csr_address_i == `CSR_CYCL_L;
assign read_cycleh = read_csr_address_i == `CSR_CYCL_H;
assign read_instret = read_csr_address_i == `CSR_INST_L;
assign read_instreth = read_csr_address_i == `CSR_INST_H;
wire [$clog2(`NUM_CSRS)-1:0] read_addr, write_addr;
// cast address to physical CSR range
assign read_addr = $size(read_addr)'(in_read_csr_address);
assign write_addr = $size(write_addr)'(in_write_csr_address);
assign read_addr = $size(read_addr)'(read_csr_address_i);
assign write_addr = $size(write_addr)'(write_csr_address_i);
// wire thread_select = in_read_csr_address == 12'h20;
// wire warp_select = in_read_csr_address == 12'h21;
// wire thread_select = read_csr_address_i == 12'h20;
// wire warp_select = read_csr_address_i == 12'h21;
// assign out_read_csr_data = thread_select ? thread_ids :
// assign read_csr_data_o = thread_select ? thread_ids :
// warp_select ? warp_ids :
// 0;
@@ -67,16 +67,16 @@ module VX_csr_data (
instret <= 0;
end else begin
cycle <= cycle + 1;
if (in_write_valid) begin
csr[write_addr] <= in_write_csr_data;
if (write_valid_i) begin
csr[write_addr] <= write_csr_data_i;
end
if (in_writeback_valid) begin
if (writeback_valid_i) begin
instret <= instret + 1;
end
end
end
assign out_read_csr_data = read_cycle ? cycle[31:0] :
assign read_csr_data_o = read_cycle ? cycle[31:0] :
read_cycleh ? cycle[63:32] :
read_instret ? instret[31:0] :
read_instreth ? instret[63:32] :