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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-20 13:52:24 -04:00
parent 94e4f056db
commit 1a2823da0d
31 changed files with 253 additions and 260 deletions
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8
hw/rtl/pipe_regs/VX_f_d_reg.v
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@@ -1,9 +1,9 @@
`include "../VX_define.vh"
module VX_f_d_reg (
input wire clk,
input wire reset,
input wire in_freeze,
input wire clk,
input wire reset,
input wire freeze_i,
VX_inst_meta_if fe_inst_meta_fd,
VX_inst_meta_if fd_inst_meta_de
@@ -11,7 +11,7 @@ module VX_f_d_reg (
);
wire flush = 1'b0;
wire stall = in_freeze == 1'b1;
wire stall = freeze_i == 1'b1;
VX_generic_register #( .N(64+`NW_BITS-1+1+`NUM_THREADS) ) f_d_reg (
.clk (clk),