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This commit is contained in:
Blaise Tine
2021-06-25 16:28:10 -07:00
parent 7e0dc81cee
commit 1ea738ed26
14 changed files with 257 additions and 538 deletions
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2
ci/regression.sh
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@@ -60,7 +60,7 @@ CONFIGS="-DMEM_BLOCK_SIZE=16 -DPLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH=128 -DPLAT
CONFIGS="-DPLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH=27" ./ci/blackbox.sh --driver=vlsim --cores=1 --app=demo
# test 128-bit DRAM block
CONFIGS="-DPLATFORM_PARAM_LOCAL_MEMORY_BANKS=1 -DPLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH=128 -DPLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH=28" ./ci/blackbox.sh --driver=vlsim --cores=1 --app=demo
CONFIGS="-DPLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH=128 -DPLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH=28 -DPLATFORM_PARAM_LOCAL_MEMORY_BANKS=1" ./ci/blackbox.sh --driver=vlsim --cores=1 --app=demo
# test verilator reset values
CONFIGS="-DVERILATOR_RESET_VALUE=0" ./ci/blackbox.sh --driver=vlsim --cores=4 --app=sgemm

2
driver/opae/vlsim/opae_sim.cpp
View File

@@ -154,6 +154,8 @@ void opae_sim::write_mmio64(uint32_t mmio_num, uint64_t offset, uint64_t value)
void opae_sim::reset() {
cci_reads_.clear();
cci_writes_.clear();
vortex_afu_->vcp2af_sRxPort_c0_mmioRdValid = 0;
vortex_afu_->vcp2af_sRxPort_c0_mmioWrValid = 0;
vortex_afu_->vcp2af_sRxPort_c0_rspValid = 0;
vortex_afu_->vcp2af_sRxPort_c1_rspValid = 0;
vortex_afu_->vcp2af_sRxPort_c0_TxAlmFull = 0;

2
hw/rtl/VX_execute.v
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@@ -16,7 +16,7 @@ module VX_execute #(
VX_cmt_to_csr_if cmt_to_csr_if,
`ifdef PERF_ENABLE
VX_perf_memsys_if perf_memsys_if,
VX_perf_memsys_if perf_memsys_if,
VX_perf_pipeline_if perf_pipeline_if,
`endif

2
hw/rtl/VX_instr_demux.v
View File

@@ -5,7 +5,7 @@ module VX_instr_demux (
input wire reset,
// inputs
VX_decode_if execute_if,
VX_instr_sched_if execute_if,
VX_gpr_rsp_if gpr_rsp_if,
// outputs

85
hw/rtl/VX_ibuffer.v → hw/rtl/VX_instr_sched.v
View File

@@ -1,16 +1,16 @@
`include "VX_define.vh"
module VX_ibuffer #(
module VX_instr_sched #(
parameter CORE_ID = 0
) (
input wire clk,
input wire reset,
// inputs
VX_decode_if ibuf_enq_if,
VX_decode_if decode_if,
// outputs
VX_decode_if ibuf_deq_if
VX_instr_sched_if instr_sched_if
);
`UNUSED_PARAM (CORE_ID)
@@ -28,13 +28,13 @@ module VX_ibuffer #(
wire [`NUM_WARPS-1:0][DATAW-1:0] q_data_prev;
reg [`NUM_WARPS-1:0][DATAW-1:0] q_data_out;
wire enq_fire = ibuf_enq_if.valid && ibuf_enq_if.ready;
wire deq_fire = ibuf_deq_if.valid && ibuf_deq_if.ready;
wire enq_fire = decode_if.valid && decode_if.ready;
wire deq_fire = instr_sched_if.valid && instr_sched_if.ready;
for (genvar i = 0; i < `NUM_WARPS; ++i) begin
wire writing = enq_fire && (i == ibuf_enq_if.wid);
wire reading = deq_fire && (i == ibuf_deq_if.wid);
wire writing = enq_fire && (i == decode_if.wid);
wire reading = deq_fire && (i == instr_sched_if.wid);
wire is_head_ptr = empty_r[i] || (alm_empty_r[i] && reading);
@@ -104,7 +104,7 @@ module VX_ibuffer #(
valid_table_n[deq_wid] = !q_alm_empty[deq_wid];
end
if (enq_fire) begin
valid_table_n[ibuf_enq_if.wid] = 1;
valid_table_n[decode_if.wid] = 1;
end
end
@@ -126,7 +126,7 @@ module VX_ibuffer #(
deq_instr_n = deq_fire ? q_data_prev[deq_wid] : q_data_out[deq_wid];
end else begin
deq_valid_n = enq_fire;
deq_wid_n = ibuf_enq_if.wid;
deq_wid_n = decode_if.wid;
deq_instr_n = q_data_in;
end
end
@@ -142,8 +142,8 @@ module VX_ibuffer #(
schedule_table_n[deq_wid_n] = 0;
end
wire warp_added = enq_fire && q_empty[ibuf_enq_if.wid];
wire warp_removed = deq_fire && ~(enq_fire && ibuf_enq_if.wid == deq_wid) && q_alm_empty[deq_wid];
wire warp_added = enq_fire && q_empty[decode_if.wid];
wire warp_removed = deq_fire && ~(enq_fire && decode_if.wid == deq_wid) && q_alm_empty[deq_wid];
always @(posedge clk) begin
if (reset) begin
@@ -166,37 +166,38 @@ module VX_ibuffer #(
deq_instr <= deq_instr_n;
end
assign ibuf_enq_if.ready = ~q_full[ibuf_enq_if.wid];
assign q_data_in = {ibuf_enq_if.tmask,
ibuf_enq_if.PC,
ibuf_enq_if.ex_type,
ibuf_enq_if.op_type,
ibuf_enq_if.op_mod,
ibuf_enq_if.wb,
ibuf_enq_if.rd,
ibuf_enq_if.rs1,
ibuf_enq_if.rs2,
ibuf_enq_if.rs3,
ibuf_enq_if.imm,
ibuf_enq_if.use_PC,
ibuf_enq_if.use_imm,
ibuf_enq_if.used_regs};
assign decode_if.ready = ~q_full[decode_if.wid];
assign q_data_in = {decode_if.tmask,
decode_if.PC,
decode_if.ex_type,
decode_if.op_type,
decode_if.op_mod,
decode_if.wb,
decode_if.rd,
decode_if.rs1,
decode_if.rs2,
decode_if.rs3,
decode_if.imm,
decode_if.use_PC,
decode_if.use_imm,
decode_if.used_regs};
assign ibuf_deq_if.valid = deq_valid;
assign ibuf_deq_if.wid = deq_wid;
assign {ibuf_deq_if.tmask,
ibuf_deq_if.PC,
ibuf_deq_if.ex_type,
ibuf_deq_if.op_type,
ibuf_deq_if.op_mod,
ibuf_deq_if.wb,
ibuf_deq_if.rd,
ibuf_deq_if.rs1,
ibuf_deq_if.rs2,
ibuf_deq_if.rs3,
ibuf_deq_if.imm,
ibuf_deq_if.use_PC,
ibuf_deq_if.use_imm,
ibuf_deq_if.used_regs} = deq_instr;
assign instr_sched_if.valid = deq_valid;
assign instr_sched_if.wid = deq_wid;
assign instr_sched_if.wid_n = deq_wid_n;
assign {instr_sched_if.tmask,
instr_sched_if.PC,
instr_sched_if.ex_type,
instr_sched_if.op_type,
instr_sched_if.op_mod,
instr_sched_if.wb,
instr_sched_if.rd,
instr_sched_if.rs1,
instr_sched_if.rs2,
instr_sched_if.rs3,
instr_sched_if.imm,
instr_sched_if.use_PC,
instr_sched_if.use_imm,
instr_sched_if.used_regs} = deq_instr;
endmodule

94
hw/rtl/VX_issue.v
View File

@@ -21,36 +21,36 @@ module VX_issue #(
VX_fpu_req_if fpu_req_if,
VX_gpu_req_if gpu_req_if
);
VX_decode_if ibuf_deq_if();
VX_decode_if execute_if();
VX_instr_sched_if instr_sched_if();
VX_instr_sched_if execute_if();
VX_gpr_req_if gpr_req_if();
VX_gpr_rsp_if gpr_rsp_if();
wire scoreboard_delay;
VX_ibuffer #(
VX_instr_sched #(
.CORE_ID(CORE_ID)
) ibuffer (
.clk (clk),
.reset (reset),
.ibuf_enq_if (decode_if),
.ibuf_deq_if (ibuf_deq_if)
) instr_sched (
.clk (clk),
.reset (reset),
.decode_if (decode_if),
.instr_sched_if (instr_sched_if)
);
VX_scoreboard #(
.CORE_ID(CORE_ID)
) scoreboard (
.clk (clk),
.reset (reset),
.ibuf_deq_if (ibuf_deq_if),
.writeback_if (writeback_if),
.delay (scoreboard_delay)
.clk (clk),
.reset (reset),
.instr_sched_if (instr_sched_if),
.writeback_if (writeback_if),
.delay (scoreboard_delay)
);
assign gpr_req_if.wid = ibuf_deq_if.wid;
assign gpr_req_if.rs1 = ibuf_deq_if.rs1;
assign gpr_req_if.rs2 = ibuf_deq_if.rs2;
assign gpr_req_if.rs3 = ibuf_deq_if.rs3;
assign gpr_req_if.wid = instr_sched_if.wid;
assign gpr_req_if.rs1 = instr_sched_if.rs1;
assign gpr_req_if.rs2 = instr_sched_if.rs2;
assign gpr_req_if.rs3 = instr_sched_if.rs3;
VX_gpr_stage #(
.CORE_ID(CORE_ID)
@@ -62,19 +62,19 @@ module VX_issue #(
.gpr_rsp_if (gpr_rsp_if)
);
assign execute_if.valid = ibuf_deq_if.valid && ~scoreboard_delay;
assign execute_if.wid = ibuf_deq_if.wid;
assign execute_if.tmask = ibuf_deq_if.tmask;
assign execute_if.PC = ibuf_deq_if.PC;
assign execute_if.ex_type = ibuf_deq_if.ex_type;
assign execute_if.op_type = ibuf_deq_if.op_type;
assign execute_if.op_mod = ibuf_deq_if.op_mod;
assign execute_if.wb = ibuf_deq_if.wb;
assign execute_if.rd = ibuf_deq_if.rd;
assign execute_if.rs1 = ibuf_deq_if.rs1;
assign execute_if.imm = ibuf_deq_if.imm;
assign execute_if.use_PC = ibuf_deq_if.use_PC;
assign execute_if.use_imm = ibuf_deq_if.use_imm;
assign execute_if.valid = instr_sched_if.valid && ~scoreboard_delay;
assign execute_if.wid = instr_sched_if.wid;
assign execute_if.tmask = instr_sched_if.tmask;
assign execute_if.PC = instr_sched_if.PC;
assign execute_if.ex_type = instr_sched_if.ex_type;
assign execute_if.op_type = instr_sched_if.op_type;
assign execute_if.op_mod = instr_sched_if.op_mod;
assign execute_if.wb = instr_sched_if.wb;
assign execute_if.rd = instr_sched_if.rd;
assign execute_if.rs1 = instr_sched_if.rs1;
assign execute_if.imm = instr_sched_if.imm;
assign execute_if.use_PC = instr_sched_if.use_PC;
assign execute_if.use_imm = instr_sched_if.use_imm;
VX_instr_demux instr_demux (
.clk (clk),
@@ -89,23 +89,23 @@ module VX_issue #(
);
// issue the instruction
assign ibuf_deq_if.ready = !scoreboard_delay && execute_if.ready;
assign instr_sched_if.ready = !scoreboard_delay && execute_if.ready;
`SCOPE_ASSIGN (issue_fire, ibuf_deq_if.valid && ibuf_deq_if.ready);
`SCOPE_ASSIGN (issue_wid, ibuf_deq_if.wid);
`SCOPE_ASSIGN (issue_tmask, ibuf_deq_if.tmask);
`SCOPE_ASSIGN (issue_pc, ibuf_deq_if.PC);
`SCOPE_ASSIGN (issue_ex_type, ibuf_deq_if.ex_type);
`SCOPE_ASSIGN (issue_op_type, ibuf_deq_if.op_type);
`SCOPE_ASSIGN (issue_op_mod, ibuf_deq_if.op_mod);
`SCOPE_ASSIGN (issue_wb, ibuf_deq_if.wb);
`SCOPE_ASSIGN (issue_rd, ibuf_deq_if.rd);
`SCOPE_ASSIGN (issue_rs1, ibuf_deq_if.rs1);
`SCOPE_ASSIGN (issue_rs2, ibuf_deq_if.rs2);
`SCOPE_ASSIGN (issue_rs3, ibuf_deq_if.rs3);
`SCOPE_ASSIGN (issue_imm, ibuf_deq_if.imm);
`SCOPE_ASSIGN (issue_use_pc, ibuf_deq_if.use_PC);
`SCOPE_ASSIGN (issue_use_imm, ibuf_deq_if.use_imm);
`SCOPE_ASSIGN (issue_fire, instr_sched_if.valid && instr_sched_if.ready);
`SCOPE_ASSIGN (issue_wid, instr_sched_if.wid);
`SCOPE_ASSIGN (issue_tmask, instr_sched_if.tmask);
`SCOPE_ASSIGN (issue_pc, instr_sched_if.PC);
`SCOPE_ASSIGN (issue_ex_type, instr_sched_if.ex_type);
`SCOPE_ASSIGN (issue_op_type, instr_sched_if.op_type);
`SCOPE_ASSIGN (issue_op_mod, instr_sched_if.op_mod);
`SCOPE_ASSIGN (issue_wb, instr_sched_if.wb);
`SCOPE_ASSIGN (issue_rd, instr_sched_if.rd);
`SCOPE_ASSIGN (issue_rs1, instr_sched_if.rs1);
`SCOPE_ASSIGN (issue_rs2, instr_sched_if.rs2);
`SCOPE_ASSIGN (issue_rs3, instr_sched_if.rs3);
`SCOPE_ASSIGN (issue_imm, instr_sched_if.imm);
`SCOPE_ASSIGN (issue_use_pc, instr_sched_if.use_PC);
`SCOPE_ASSIGN (issue_use_imm, instr_sched_if.use_imm);
`SCOPE_ASSIGN (scoreboard_delay, scoreboard_delay);
`SCOPE_ASSIGN (execute_delay, ~execute_if.ready);
`SCOPE_ASSIGN (gpr_rsp_a, gpr_rsp_if.rs1_data);
@@ -145,7 +145,7 @@ module VX_issue #(
if (decode_if.valid & !decode_if.ready) begin
perf_ibf_stalls <= perf_ibf_stalls + `PERF_CTR_BITS'd1;
end
if (ibuf_deq_if.valid & scoreboard_delay) begin
if (instr_sched_if.valid & scoreboard_delay) begin
perf_scb_stalls <= perf_scb_stalls + `PERF_CTR_BITS'd1;
end
if (alu_req_if.valid & !alu_req_if.ready) begin

73
hw/rtl/VX_scoreboard.v
View File

@@ -6,58 +6,65 @@ module VX_scoreboard #(
input wire clk,
input wire reset,
VX_decode_if ibuf_deq_if,
VX_instr_sched_if instr_sched_if,
VX_writeback_if writeback_if,
output wire delay
);
reg [`NUM_WARPS-1:0][`NUM_REGS-1:0] inuse_regs;
reg [`NUM_WARPS-1:0][`NUM_REGS-1:0] inuse_regs, inuse_regs_n;
wire [`NUM_REGS-1:0] deq_inuse_regs = inuse_regs[ibuf_deq_if.wid];
reg [`NUM_REGS-1:0] deq_inuse_regs;
assign delay = | (deq_inuse_regs & ibuf_deq_if.used_regs);
assign delay = |(deq_inuse_regs & instr_sched_if.used_regs);
wire reserve_reg = ibuf_deq_if.valid && ibuf_deq_if.ready && ibuf_deq_if.wb;
wire reserve_reg = instr_sched_if.valid && instr_sched_if.ready && instr_sched_if.wb;
wire release_reg = writeback_if.valid && writeback_if.ready && writeback_if.eop;
always @(posedge clk) begin
if (reset) begin
inuse_regs <= (`NUM_WARPS*`NUM_REGS)'(0);
end else begin
if (reserve_reg) begin
inuse_regs[ibuf_deq_if.wid][ibuf_deq_if.rd] <= 1;
end
if (release_reg) begin
inuse_regs[writeback_if.wid][writeback_if.rd] <= 0;
assert(inuse_regs[writeback_if.wid][writeback_if.rd] != 0)
else $error("%t: *** core%0d: invalid writeback register: wid=%0d, PC=%0h, rd=%0d",
$time, CORE_ID, writeback_if.wid, writeback_if.PC, writeback_if.rd);
end
always @(*) begin
inuse_regs_n = inuse_regs;
if (reserve_reg) begin
inuse_regs_n[instr_sched_if.wid][instr_sched_if.rd] = 1;
end
if (release_reg) begin
inuse_regs_n[writeback_if.wid][writeback_if.rd] = 0;
end
end
`ifdef DBG_PRINT_PIPELINE
always @(posedge clk) begin
if (ibuf_deq_if.valid && ~ibuf_deq_if.ready) begin
$display("%t: *** core%0d-stall: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b",
$time, CORE_ID, ibuf_deq_if.wid, ibuf_deq_if.PC, ibuf_deq_if.rd, ibuf_deq_if.wb,
deq_inuse_regs[ibuf_deq_if.rd], deq_inuse_regs[ibuf_deq_if.rs1], deq_inuse_regs[ibuf_deq_if.rs2], deq_inuse_regs[ibuf_deq_if.rs3]);
if (reset) begin
inuse_regs <= '0;
end else begin
inuse_regs <= inuse_regs_n;
end
end
`endif
deq_inuse_regs <= inuse_regs_n[instr_sched_if.wid_n];
end
reg [31:0] deadlock_ctr;
wire [31:0] deadlock_timeout = 1000 * (10 ** (`L2_ENABLE + `L3_ENABLE));
always @(posedge clk) begin
if (reset) begin
deadlock_ctr <= 0;
end else if (ibuf_deq_if.valid && ~ibuf_deq_if.ready) begin
deadlock_ctr <= deadlock_ctr + 1;
assert(deadlock_ctr < deadlock_timeout) else $error("%t: *** core%0d-deadlock: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b",
$time, CORE_ID, ibuf_deq_if.wid, ibuf_deq_if.PC, ibuf_deq_if.rd, ibuf_deq_if.wb,
deq_inuse_regs[ibuf_deq_if.rd], deq_inuse_regs[ibuf_deq_if.rs1], deq_inuse_regs[ibuf_deq_if.rs2], deq_inuse_regs[ibuf_deq_if.rs3]);
end else if (ibuf_deq_if.valid && ibuf_deq_if.ready) begin
deadlock_ctr <= 0;
end else begin
`ifdef DBG_PRINT_PIPELINE
if (instr_sched_if.valid && ~instr_sched_if.ready) begin
$display("%t: *** core%0d-stall: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b",
$time, CORE_ID, instr_sched_if.wid, instr_sched_if.PC, instr_sched_if.rd, instr_sched_if.wb,
deq_inuse_regs[instr_sched_if.rd], deq_inuse_regs[instr_sched_if.rs1], deq_inuse_regs[instr_sched_if.rs2], deq_inuse_regs[instr_sched_if.rs3]);
end
`endif
if (release_reg) begin
assert(inuse_regs[writeback_if.wid][writeback_if.rd] != 0)
else $error("%t: *** core%0d: invalid writeback register: wid=%0d, PC=%0h, rd=%0d",
$time, CORE_ID, writeback_if.wid, writeback_if.PC, writeback_if.rd);
end
if (instr_sched_if.valid && ~instr_sched_if.ready) begin
deadlock_ctr <= deadlock_ctr + 1;
assert(deadlock_ctr < deadlock_timeout) else $error("%t: *** core%0d-deadlock: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b",
$time, CORE_ID, instr_sched_if.wid, instr_sched_if.PC, instr_sched_if.rd, instr_sched_if.wb,
deq_inuse_regs[instr_sched_if.rd], deq_inuse_regs[instr_sched_if.rs1], deq_inuse_regs[instr_sched_if.rs2], deq_inuse_regs[instr_sched_if.rs3]);
end else if (instr_sched_if.valid && instr_sched_if.ready) begin
deadlock_ctr <= 0;
end
end
end

8
hw/rtl/afu/vortex_afu.sv
View File

@@ -718,6 +718,9 @@ always @(posedge clk) begin
if (cci_rd_rsp_fire) begin
cci_rd_rsp_ctr <= cci_rd_rsp_ctr + CCI_RD_QUEUE_TAGW'(1);
if (CCI_RD_QUEUE_TAGW'(cci_rd_rsp_ctr) == CCI_RD_QUEUE_TAGW'(CCI_RD_WINDOW_SIZE-1)) begin
cci_mem_wr_req_addr_base <= cci_mem_wr_req_addr_base + CCI_ADDR_WIDTH'(CCI_RD_WINDOW_SIZE);
end
`ifdef DBG_PRINT_OPAE
$display("%t: CCI Rd Rsp: idx=%0d, ctr=%0d, data=%0h", $time, cci_rd_rsp_tag, cci_rd_rsp_ctr, cp2af_sRxPort.c0.data);
`endif
@@ -729,10 +732,7 @@ always @(posedge clk) begin
`endif
end
if (cci_mem_wr_req_fire) begin
if (CCI_RD_QUEUE_TAGW'(cci_mem_wr_req_ctr) == CCI_RD_QUEUE_TAGW'(CCI_RD_WINDOW_SIZE-1)) begin
cci_mem_wr_req_addr_base <= cci_mem_wr_req_addr_base + CCI_ADDR_WIDTH'(CCI_RD_WINDOW_SIZE);
end
if (cci_mem_wr_req_fire) begin
cci_mem_wr_req_ctr <= cci_mem_wr_req_ctr + CCI_ADDR_WIDTH'(1);
if (cci_mem_wr_req_ctr == (cmd_data_size-1)) begin
cmd_write_done <= 1;

202
hw/rtl/cache/VX_nc_bypass.v vendored
View File

@@ -93,42 +93,37 @@ module VX_nc_bypass #(
// core request handling
reg [NUM_REQS-1:0] core_req_valid_out_r;
reg [NUM_REQS-1:0] core_req_ready_in_r;
wire [NUM_REQS-1:0] core_req_valid_in_nc;
wire [NUM_REQS-1:0] core_req_nc_sel;
wire [NUM_REQS-1:0] core_req_nc_tids;
wire [`UP(CORE_REQ_TIDW)-1:0] core_req_nc_tid;
wire core_req_nc_valid;
for (genvar i = 0; i < NUM_REQS; ++i) begin
assign core_req_valid_in_nc[i] = core_req_valid_in[i] && core_req_tag_in[i][NC_TAG_BIT];
assign core_req_nc_tids[i] = core_req_tag_in[i][NC_TAG_BIT];
end
always @(*) begin
for (integer i = 0; i < NUM_REQS; ++i) begin
if (core_req_valid_in_nc[i]) begin
core_req_valid_out_r[i] = 0;
end else begin
core_req_valid_out_r[i] = core_req_valid_in[i];
end
end
end
wire [`UP(CORE_REQ_TIDW)-1:0] core_req_nc_tid;
wire core_req_nc_valid;
assign core_req_valid_in_nc = core_req_valid_in & core_req_nc_tids;
VX_priority_encoder #(
.N (NUM_REQS)
) core_req_sel (
.data_in (core_req_valid_in_nc),
.index (core_req_nc_tid),
`UNUSED_PIN (onehot),
.onehot (core_req_nc_sel),
.valid_out (core_req_nc_valid)
);
assign core_req_valid_out = core_req_valid_in & ~core_req_nc_tids;
`UNUSED_VAR (core_req_nc_sel)
if (NUM_REQS > 1) begin
always @(*) begin
for (integer i = 0; i < NUM_REQS; ++i) begin
if (core_req_valid_in_nc[i]) begin
core_req_ready_in_r[i] = mem_req_ready_out && (core_req_nc_tid == CORE_REQ_TIDW'(i));
core_req_ready_in_r[i] = ~mem_req_valid_in && mem_req_ready_out && core_req_nc_sel[i];
end else begin
core_req_ready_in_r[i] = core_req_ready_out[i];
end
@@ -138,14 +133,13 @@ module VX_nc_bypass #(
`UNUSED_VAR (core_req_nc_tid)
always @(*) begin
if (core_req_valid_in_nc) begin
core_req_ready_in_r = mem_req_ready_out;
core_req_ready_in_r = ~mem_req_valid_in && mem_req_ready_out;
end else begin
core_req_ready_in_r = core_req_ready_out;
end
end
end
assign core_req_valid_out = core_req_valid_out_r;
assign core_req_rw_out = core_req_rw_in;
assign core_req_addr_out = core_req_addr_in;
assign core_req_byteen_out = core_req_byteen_in;
@@ -161,91 +155,91 @@ module VX_nc_bypass #(
reg [MEM_ADDR_WIDTH-1:0] mem_req_addr_out_r;
reg [MEM_DATA_WIDTH-1:0] mem_req_data_out_r;
reg [MEM_TAG_WIDTH-1:0] mem_req_tag_out_r;
reg mem_req_ready_in_r;
reg mem_req_ready_in_r;
always @(*) begin
if (core_req_nc_valid) begin
if (mem_req_valid_in) begin
mem_req_valid_out_r = 1;
mem_req_ready_in_r = 0;
end else begin
mem_req_valid_out_r = mem_req_valid_in;
mem_req_ready_in_r = mem_req_ready_out;
end else begin
mem_req_valid_out_r = core_req_nc_valid;
mem_req_ready_in_r = 0;
end
end
if (NUM_REQS > 1) begin
always @(*) begin
if (core_req_nc_valid) begin
if (mem_req_valid_in) begin
mem_req_rw_out_r = mem_req_rw_in;
mem_req_addr_out_r = mem_req_addr_in;
mem_req_data_out_r = mem_req_data_in;
end else begin
mem_req_rw_out_r = core_req_rw_in[core_req_nc_tid];
mem_req_addr_out_r = core_req_addr_in[core_req_nc_tid][D +: MEM_ADDR_WIDTH];
for (integer i = 0; i < P; ++i) begin
mem_req_data_out_r[i * CORE_DATA_WIDTH +: CORE_DATA_WIDTH] = core_req_data_in[core_req_nc_tid];
end
end else begin
mem_req_rw_out_r = mem_req_rw_in;
mem_req_addr_out_r = mem_req_addr_in;
mem_req_data_out_r = mem_req_data_in;
end
end
if (D != 0) begin
wire [D-1:0] req_addr_idx = core_req_addr_in[core_req_nc_tid][D-1:0];
always @(*) begin
if (core_req_nc_valid) begin
if (mem_req_valid_in) begin
mem_req_byteen_out_r = mem_req_byteen_in;
mem_req_tag_out_r = mem_req_tag_in;
end else begin
mem_req_byteen_out_r = 0;
mem_req_byteen_out_r[req_addr_idx * CORE_DATA_SIZE +: CORE_DATA_SIZE] = core_req_byteen_in[core_req_nc_tid];
mem_req_tag_out_r = MEM_TAG_WIDTH'({core_req_nc_tid, req_addr_idx, core_req_tag_in[core_req_nc_tid]});
end else begin
mem_req_byteen_out_r = mem_req_byteen_in;
mem_req_tag_out_r = mem_req_tag_in;
end
end
end else begin
always @(*) begin
if (core_req_nc_valid) begin
mem_req_byteen_out_r = core_req_byteen_in[core_req_nc_tid];
mem_req_tag_out_r = MEM_TAG_WIDTH'({core_req_nc_tid, core_req_tag_in[core_req_nc_tid]});
end else begin
if (mem_req_valid_in) begin
mem_req_byteen_out_r = mem_req_byteen_in;
mem_req_tag_out_r = mem_req_tag_in;
end else begin
mem_req_byteen_out_r = core_req_byteen_in[core_req_nc_tid];
mem_req_tag_out_r = MEM_TAG_WIDTH'({core_req_nc_tid, core_req_tag_in[core_req_nc_tid]});
end
end
end
end else begin
always @(*) begin
if (core_req_nc_valid) begin
if (mem_req_valid_in) begin
mem_req_rw_out_r = mem_req_rw_in;
mem_req_addr_out_r = mem_req_addr_in;
mem_req_data_out_r = mem_req_data_in;
end else begin
mem_req_rw_out_r = core_req_rw_in;
mem_req_addr_out_r = core_req_addr_in[0][D +: MEM_ADDR_WIDTH];
for (integer i = 0; i < P; ++i) begin
mem_req_data_out_r[i * CORE_DATA_WIDTH +: CORE_DATA_WIDTH] = core_req_data_in;
end
end else begin
mem_req_rw_out_r = mem_req_rw_in;
mem_req_addr_out_r = mem_req_addr_in;
mem_req_data_out_r = mem_req_data_in;
end
end
if (D != 0) begin
wire [D-1:0] req_addr_idx = core_req_addr_in[0][D-1:0];
always @(*) begin
if (core_req_nc_valid) begin
if (mem_req_valid_in) begin
mem_req_byteen_out_r = mem_req_byteen_in;
mem_req_tag_out_r = mem_req_tag_in;
end else begin
mem_req_byteen_out_r = 0;
mem_req_byteen_out_r[req_addr_idx * CORE_DATA_SIZE +: CORE_DATA_SIZE] = core_req_byteen_in;
mem_req_tag_out_r = MEM_TAG_WIDTH'({req_addr_idx, core_req_tag_in});
end else begin
mem_req_byteen_out_r = mem_req_byteen_in;
mem_req_tag_out_r = mem_req_tag_in;
end
end
end else begin
always @(*) begin
if (core_req_nc_valid) begin
mem_req_byteen_out_r = core_req_byteen_in;
mem_req_tag_out_r = MEM_TAG_WIDTH'(core_req_tag_in);
end else begin
if (mem_req_valid_in) begin
mem_req_byteen_out_r = mem_req_byteen_in;
mem_req_tag_out_r = mem_req_tag_in;
end else begin
mem_req_byteen_out_r = core_req_byteen_in;
mem_req_tag_out_r = MEM_TAG_WIDTH'(core_req_tag_in);
end
end
end
@@ -272,26 +266,25 @@ module VX_nc_bypass #(
wire [CORE_REQ_TIDW-1:0] rsp_tid = mem_rsp_tag_in[(CORE_TAG_WIDTH + D) +: CORE_REQ_TIDW];
if (NUM_RSP_TAGS > 1) begin
always @(*) begin
for (integer i = 0; i < NUM_REQS; ++i) begin
if (is_mem_rsp_nc && (rsp_tid == CORE_REQ_TIDW'(i))) begin
core_rsp_valid_out_r[i] = 1;
core_rsp_tag_out_r[i] = mem_rsp_tag_in[CORE_TAG_WIDTH-1:0];
core_rsp_ready_in_r[i] = 0;
end else begin
core_rsp_valid_out_r[i] = core_rsp_valid_in[i];
core_rsp_tag_out_r[i] = core_rsp_tag_in[i];
core_rsp_ready_in_r[i] = core_rsp_ready_out[i];
if (is_mem_rsp_nc) begin
core_rsp_valid_out_r = 0;
core_rsp_valid_out_r[rsp_tid] = 1;
for (integer i = 0; i < NUM_REQS; ++i) begin
core_rsp_tag_out_r[i] = mem_rsp_tag_in[CORE_TAG_WIDTH-1:0];
end
end
core_rsp_ready_in_r = 0;
end else begin
core_rsp_valid_out_r = core_rsp_valid_in;
core_rsp_tag_out_r = core_rsp_tag_in;
core_rsp_ready_in_r = core_rsp_ready_out;
end
end
end else begin
always @(*) begin
if (is_mem_rsp_nc) begin
core_rsp_valid_out_r = 0;
core_rsp_valid_out_r[rsp_tid] = 1;
for (integer i = 0; i < NUM_RSP_TAGS; ++i) begin
core_rsp_tag_out_r[i] = mem_rsp_tag_in[CORE_TAG_WIDTH-1:0];
end
core_rsp_tag_out_r = mem_rsp_tag_in[CORE_TAG_WIDTH-1:0];
core_rsp_ready_in_r = 0;
end else begin
core_rsp_valid_out_r = core_rsp_valid_in;
@@ -301,7 +294,7 @@ module VX_nc_bypass #(
end
end
end else begin
always @(*) begin
always @(*) begin
if (is_mem_rsp_nc) begin
core_rsp_valid_out_r = 1;
core_rsp_tag_out_r = mem_rsp_tag_in[CORE_TAG_WIDTH-1:0];
@@ -316,49 +309,23 @@ module VX_nc_bypass #(
if (D != 0) begin
wire [D-1:0] rsp_addr_idx = mem_rsp_tag_in[CORE_TAG_WIDTH +: D];
if (NUM_RSP_TAGS > 1) begin
wire [CORE_REQ_TIDW-1:0] rsp_tid = mem_rsp_tag_in[(CORE_TAG_WIDTH + D) +: CORE_REQ_TIDW];
always @(*) begin
always @(*) begin
if (is_mem_rsp_nc) begin
for (integer i = 0; i < NUM_REQS; ++i) begin
if (is_mem_rsp_nc && (rsp_tid == CORE_REQ_TIDW'(i))) begin
core_rsp_data_out_r[i] = mem_rsp_data_in[rsp_addr_idx * CORE_DATA_WIDTH +: CORE_DATA_WIDTH];
end else begin
core_rsp_data_out_r[i] = core_rsp_data_in[i];
end
end
end
end else begin
always @(*) begin
if (is_mem_rsp_nc) begin
for (integer i = 0; i < NUM_REQS; ++i) begin
core_rsp_data_out_r[i] = mem_rsp_data_in[rsp_addr_idx * CORE_DATA_WIDTH +: CORE_DATA_WIDTH];
end
end else begin
core_rsp_data_out_r = core_rsp_data_in;
core_rsp_data_out_r[i] = mem_rsp_data_in[rsp_addr_idx * CORE_DATA_WIDTH +: CORE_DATA_WIDTH];
end
end else begin
core_rsp_data_out_r = core_rsp_data_in;
end
end
end else begin
if (NUM_RSP_TAGS > 1) begin
wire [CORE_REQ_TIDW-1:0] rsp_tid = mem_rsp_tag_in[(CORE_TAG_WIDTH + D) +: CORE_REQ_TIDW];
always @(*) begin
end else begin
always @(*) begin
if (is_mem_rsp_nc) begin
for (integer i = 0; i < NUM_REQS; ++i) begin
if (is_mem_rsp_nc && (rsp_tid == CORE_REQ_TIDW'(i))) begin
core_rsp_data_out_r[i] = mem_rsp_data_in;
end else begin
core_rsp_data_out_r[i] = core_rsp_data_in[i];
end
end
end
end else begin
always @(*) begin
if (is_mem_rsp_nc) begin
for (integer i = 0; i < NUM_REQS; ++i) begin
core_rsp_data_out_r[i] = mem_rsp_data_in;
end
end else begin
core_rsp_data_out_r = core_rsp_data_in;
core_rsp_data_out_r[i] = mem_rsp_data_in;
end
end else begin
core_rsp_data_out_r = core_rsp_data_in;
end
end
end
@@ -370,39 +337,16 @@ module VX_nc_bypass #(
// memory response handling
reg mem_rsp_valid_out_r;
reg mem_rsp_ready_in_r;
always @(*) begin
if (is_mem_rsp_nc) begin
mem_rsp_valid_out_r = 0;
end else begin
mem_rsp_valid_out_r = mem_rsp_valid_in;
end
end
assign mem_rsp_valid_out = mem_rsp_valid_in && ~mem_rsp_tag_in[NC_TAG_BIT];
if (NUM_RSP_TAGS > 1) begin
wire [CORE_REQ_TIDW-1:0] rsp_tid = mem_rsp_tag_in[(CORE_TAG_WIDTH + D) +: CORE_REQ_TIDW];
always @(*) begin
if (is_mem_rsp_nc) begin
mem_rsp_ready_in_r = core_rsp_ready_out[rsp_tid];
end else begin
mem_rsp_ready_in_r = mem_rsp_ready_out;
end
end
assign mem_rsp_ready_in = is_mem_rsp_nc ? core_rsp_ready_out[rsp_tid] : mem_rsp_ready_out;
end else begin
always @(*) begin
if (is_mem_rsp_nc) begin
mem_rsp_ready_in_r = core_rsp_ready_out;
end else begin
mem_rsp_ready_in_r = mem_rsp_ready_out;
end
end
assign mem_rsp_ready_in = is_mem_rsp_nc ? core_rsp_ready_out : mem_rsp_ready_out;
end
assign mem_rsp_valid_out = mem_rsp_valid_out_r;
assign mem_rsp_data_out = mem_rsp_data_in;
assign mem_rsp_tag_out = mem_rsp_tag_in;
assign mem_rsp_ready_in = mem_rsp_ready_in_r;
assign mem_rsp_data_out = mem_rsp_data_in;
assign mem_rsp_tag_out = mem_rsp_tag_in;
endmodule

29
hw/rtl/interfaces/VX_instr_sched_if.v Normal file
View File

@@ -0,0 +1,29 @@
`ifndef VX_INSTR_SCHED_IF
`define VX_INSTR_SCHED_IF
`include "VX_define.vh"
interface VX_instr_sched_if ();
wire valid;
wire [`NW_BITS-1:0] wid;
wire [`NW_BITS-1:0] wid_n;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
wire [`EX_BITS-1:0] ex_type;
wire [`OP_BITS-1:0] op_type;
wire [`MOD_BITS-1:0] op_mod;
wire wb;
wire [`NR_BITS-1:0] rd;
wire [`NR_BITS-1:0] rs1;
wire [`NR_BITS-1:0] rs2;
wire [`NR_BITS-1:0] rs3;
wire [31:0] imm;
wire use_PC;
wire use_imm;
wire [`NUM_REGS-1:0] used_regs;
wire ready;
endinterface
`endif

121
hw/rtl/libs/VX_onehot_encoder.v
View File

@@ -23,126 +23,7 @@ module VX_onehot_encoder #(
assign data_out = data_in[!REVERSE];
assign valid = (| data_in);
end else if (N == 4) begin
reg [LN-1:0] index_r;
if (REVERSE) begin
always @(*) begin
casez (data_in)
4'b1000: index_r = LN'(0);
4'b?100: index_r = LN'(1);
4'b??10: index_r = LN'(2);
4'b???1: index_r = LN'(3);
default: index_r = 'x;
endcase
end
end else begin
always @(*) begin
casez (data_in)
4'b0001: index_r = LN'(0);
4'b001?: index_r = LN'(1);
4'b01??: index_r = LN'(2);
4'b1???: index_r = LN'(3);
default: index_r = 'x;
endcase
end
end
assign data_out = index_r;
assign valid = (| data_in);
end else if (N == 8) begin
reg [LN-1:0] index_r;
if (REVERSE) begin
always @(*) begin
casez (data_in)
8'b10000000: index_r = LN'(0);
8'b?1000000: index_r = LN'(1);
8'b??100000: index_r = LN'(2);
8'b???10000: index_r = LN'(3);
8'b????1000: index_r = LN'(4);
8'b?????100: index_r = LN'(5);
8'b??????10: index_r = LN'(6);
8'b???????1: index_r = LN'(7);
default: index_r = 'x;
endcase
end
end else begin
always @(*) begin
casez (data_in)
8'b00000001: index_r = LN'(0);
8'b0000001?: index_r = LN'(1);
8'b000001??: index_r = LN'(2);
8'b00001???: index_r = LN'(3);
8'b0001????: index_r = LN'(4);
8'b001?????: index_r = LN'(5);
8'b01??????: index_r = LN'(6);
8'b1???????: index_r = LN'(7);
default: index_r = 'x;
endcase
end
end
assign data_out = index_r;
assign valid = (| data_in);
end else if (N == 16) begin
reg [LN-1:0] index_r;
if (REVERSE) begin
always @(*) begin
casez (data_in)
16'b1000000000000000: index_r = LN'(0);
16'b?100000000000000: index_r = LN'(1);
16'b??10000000000000: index_r = LN'(2);
16'b???1000000000000: index_r = LN'(3);
16'b????100000000000: index_r = LN'(4);
16'b?????10000000000: index_r = LN'(5);
16'b??????1000000000: index_r = LN'(6);
16'b???????100000000: index_r = LN'(7);
16'b????????10000000: index_r = LN'(8);
16'b?????????1000000: index_r = LN'(9);
16'b??????????100000: index_r = LN'(10);
16'b???????????10000: index_r = LN'(11);
16'b????????????1000: index_r = LN'(12);
16'b?????????????100: index_r = LN'(13);
16'b??????????????10: index_r = LN'(14);
16'b???????????????1: index_r = LN'(15);
default: index_r = 'x;
endcase
end
end else begin
always @(*) begin
casez (data_in)
16'b0000000000000001: index_r = LN'(0);
16'b000000000000001?: index_r = LN'(1);
16'b00000000000001??: index_r = LN'(2);
16'b0000000000001???: index_r = LN'(3);
16'b000000000001????: index_r = LN'(4);
16'b00000000001?????: index_r = LN'(5);
16'b0000000001??????: index_r = LN'(6);
16'b000000001???????: index_r = LN'(7);
16'b00000001????????: index_r = LN'(8);
16'b0000001?????????: index_r = LN'(9);
16'b000001??????????: index_r = LN'(10);
16'b00001???????????: index_r = LN'(11);
16'b0001????????????: index_r = LN'(12);
16'b001?????????????: index_r = LN'(13);
16'b01??????????????: index_r = LN'(14);
16'b1???????????????: index_r = LN'(15);
default: index_r = 'x;
endcase
end
end
assign data_out = index_r;
assign valid = (| data_in);
end if (FAST) begin
end else if (FAST) begin
`IGNORE_WARNINGS_BEGIN
localparam levels_lp = $clog2(N);
localparam aligned_width_lp = 1 << $clog2(N);

125
hw/rtl/libs/VX_priority_encoder.v
View File

@@ -24,128 +24,6 @@ module VX_priority_encoder #(
assign index = ~data_in[REVERSE];
assign valid_out = (| data_in);
end else if (N == 4) begin
reg [LN-1:0] index_r;
reg [N-1:0] onehot_r;
if (REVERSE) begin
always @(*) begin
casez (data_in)
4'b1???: begin onehot_r = 4'b0001; index_r = LN'(0); end
4'b01??: begin onehot_r = 4'b0010; index_r = LN'(1); end
4'b001?: begin onehot_r = 4'b0100; index_r = LN'(2); end
4'b0001: begin onehot_r = 4'b1000; index_r = LN'(3); end
default: begin onehot_r = 'x; index_r = 'x; end
endcase
end
end else begin
always @(*) begin
casez (data_in)
4'b???1: begin onehot_r = 4'b0001; index_r = LN'(0); end
4'b??10: begin onehot_r = 4'b0010; index_r = LN'(1); end
4'b?100: begin onehot_r = 4'b0100; index_r = LN'(2); end
4'b1000: begin onehot_r = 4'b1000; index_r = LN'(3); end
default: begin onehot_r = 'x; index_r = 'x; end
endcase
end
end
assign index = index_r;
assign onehot = onehot_r;
end else if (N == 8) begin
reg [LN-1:0] index_r;
reg [N-1:0] onehot_r;
if (REVERSE) begin
always @(*) begin
casez (data_in)
8'b1???????: begin onehot_r = 8'b00000001; index_r = LN'(0); end
8'b01??????: begin onehot_r = 8'b00000010; index_r = LN'(1); end
8'b001?????: begin onehot_r = 8'b00000100; index_r = LN'(2); end
8'b0001????: begin onehot_r = 8'b00001000; index_r = LN'(3); end
8'b00001???: begin onehot_r = 8'b00010000; index_r = LN'(4); end
8'b000001??: begin onehot_r = 8'b00100000; index_r = LN'(5); end
8'b0000001?: begin onehot_r = 8'b01000000; index_r = LN'(6); end
8'b00000001: begin onehot_r = 8'b10000000; index_r = LN'(7); end
default: begin onehot_r = 'x; index_r = 'x; end
endcase
end
end else begin
always @(*) begin
casez (data_in)
8'b???????1: begin onehot_r = 8'b00000001; index_r = LN'(0); end
8'b??????10: begin onehot_r = 8'b00000010; index_r = LN'(1); end
8'b?????100: begin onehot_r = 8'b00000100; index_r = LN'(2); end
8'b????1000: begin onehot_r = 8'b00001000; index_r = LN'(3); end
8'b???10000: begin onehot_r = 8'b00010000; index_r = LN'(4); end
8'b??100000: begin onehot_r = 8'b00100000; index_r = LN'(5); end
8'b?1000000: begin onehot_r = 8'b01000000; index_r = LN'(6); end
8'b10000000: begin onehot_r = 8'b10000000; index_r = LN'(7); end
default: begin onehot_r = 'x; index_r = 'x; end
endcase
end
end
assign index = index_r;
assign onehot = onehot_r;
end else if (N == 16) begin
reg [LN-1:0] index_r;
reg [N-1:0] onehot_r;
if (REVERSE) begin
always @(*) begin
casez (data_in)
16'b1???????????????: begin onehot_r = 16'b0000000000000001; index_r = LN'(0); end
16'b01??????????????: begin onehot_r = 16'b0000000000000010; index_r = LN'(1); end
16'b001?????????????: begin onehot_r = 16'b0000000000000100; index_r = LN'(2); end
16'b0001????????????: begin onehot_r = 16'b0000000000001000; index_r = LN'(3); end
16'b00001???????????: begin onehot_r = 16'b0000000000010000; index_r = LN'(4); end
16'b000001??????????: begin onehot_r = 16'b0000000000100000; index_r = LN'(5); end
16'b0000001?????????: begin onehot_r = 16'b0000000001000000; index_r = LN'(6); end
16'b00000001????????: begin onehot_r = 16'b0000000010000000; index_r = LN'(7); end
16'b000000001???????: begin onehot_r = 16'b0000000100000000; index_r = LN'(8); end
16'b0000000001??????: begin onehot_r = 16'b0000001000000000; index_r = LN'(9); end
16'b00000000001?????: begin onehot_r = 16'b0000010000000000; index_r = LN'(10); end
16'b000000000001????: begin onehot_r = 16'b0000100000000000; index_r = LN'(11); end
16'b0000000000001???: begin onehot_r = 16'b0001000000000000; index_r = LN'(12); end
16'b00000000000001??: begin onehot_r = 16'b0010000000000000; index_r = LN'(13); end
16'b000000000000001?: begin onehot_r = 16'b0100000000000000; index_r = LN'(14); end
16'b0000000000000001: begin onehot_r = 16'b1000000000000000; index_r = LN'(15); end
default: begin onehot_r = 'x; index_r = 'x; end
endcase
end
end else begin
always @(*) begin
casez (data_in)
16'b???????????????1: begin onehot_r = 16'b0000000000000001; index_r = LN'(0); end
16'b??????????????10: begin onehot_r = 16'b0000000000000010; index_r = LN'(1); end
16'b?????????????100: begin onehot_r = 16'b0000000000000100; index_r = LN'(2); end
16'b????????????1000: begin onehot_r = 16'b0000000000001000; index_r = LN'(3); end
16'b???????????10000: begin onehot_r = 16'b0000000000010000; index_r = LN'(4); end
16'b??????????100000: begin onehot_r = 16'b0000000000100000; index_r = LN'(5); end
16'b?????????1000000: begin onehot_r = 16'b0000000001000000; index_r = LN'(6); end
16'b????????10000000: begin onehot_r = 16'b0000000010000000; index_r = LN'(7); end
16'b???????100000000: begin onehot_r = 16'b0000000100000000; index_r = LN'(8); end
16'b??????1000000000: begin onehot_r = 16'b0000001000000000; index_r = LN'(9); end
16'b?????10000000000: begin onehot_r = 16'b0000010000000000; index_r = LN'(10); end
16'b????100000000000: begin onehot_r = 16'b0000100000000000; index_r = LN'(11); end
16'b???1000000000000: begin onehot_r = 16'b0001000000000000; index_r = LN'(12); end
16'b??10000000000000: begin onehot_r = 16'b0010000000000000; index_r = LN'(13); end
16'b?100000000000000: begin onehot_r = 16'b0100000000000000; index_r = LN'(14); end
16'b1000000000000000: begin onehot_r = 16'b1000000000000000; index_r = LN'(15); end
default: begin onehot_r = 'x; index_r = 'x; end
endcase
end
end
assign index = index_r;
assign onehot = onehot_r;
end else if (FAST) begin
wire [N-1:0] scan_lo;
@@ -209,9 +87,8 @@ module VX_priority_encoder #(
assign index = index_r;
assign onehot = onehot_r;
assign valid_out = (| data_in);
end
assign valid_out = (| data_in);
endmodule

21
hw/rtl/libs/VX_rr_arbiter.v
View File

@@ -14,8 +14,6 @@ module VX_rr_arbiter #(
output wire grant_valid
);
localparam NN = NUM_REQS * NUM_REQS;
if (NUM_REQS == 1) begin
`UNUSED_VAR (clk)
@@ -399,17 +397,14 @@ module VX_rr_arbiter #(
always @(*) begin
grant_index_r = 'x;
grant_onehot_r = 'x;
for (integer i = 0; i < NN; ++i) begin
/* verilator lint_off UNUSED */
integer src = i / NUM_REQS;
integer dst = i % NUM_REQS;
integer next = (dst + 1) % NUM_REQS;
/* verilator lint_on UNUSED */
if (state == LOG_NUM_REQS'(src )
&& requests[next]) begin
grant_index_r = LOG_NUM_REQS'(next);
grant_onehot_r = '0;
grant_onehot_r[next] = 1;
for (integer i = 0; i < NUM_REQS; ++i) begin
for (integer j = 0; j < NUM_REQS; ++j) begin
if (state == LOG_NUM_REQS'(i)
&& requests[(j + 1) % NUM_REQS]) begin
grant_index_r = LOG_NUM_REQS'((j + 1) % NUM_REQS);
grant_onehot_r = '0;
grant_onehot_r[(j + 1) % NUM_REQS] = 1;
end
end
end
end

29
hw/syn/quartus/project.tcl
View File

@@ -40,30 +40,13 @@ set_global_assignment -name VERILOG_MACRO SYNTHESIS
set_global_assignment -name VERILOG_MACRO NDEBUG
set_global_assignment -name MESSAGE_DISABLE 16818
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name OPTIMIZATION_TECHNIQUE AREA
#set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
#set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
#set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
#set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0
#set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
#set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
#set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
#set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
#set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
#set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
#set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
#set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
#set_global_assignment -name USE_HIGH_SPEED_ADDER ON
#set_global_assignment -name MUX_RESTRUCTURE ON
#set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
#set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "FORCE ALL TILES WITH FAILING TIMING PATHS TO HIGH SPEED"
#set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
#set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
#set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
#set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
#set_global_assignment -name SEED 1
# Power estimation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
switch $opts(family) {
"Arria 10" {