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fix RTL code undefined variables

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This commit is contained in:
Blaise Tine
2020-04-03 22:59:40 -07:00
parent 41f3245376
commit 1f63139ce5
7 changed files with 86 additions and 47 deletions
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27
driver/hw/Makefile
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@@ -1,35 +1,36 @@
BUILD_DIR=build_ase
ASE_BUILD_DIR=build_ase
FPGA_BUILD_DIR=build_fpga
all: ase fpga
ase: setup-ase
make -C $(BUILD_DIR)
make -C $(ASE_BUILD_DIR)
fpga: setup-fpga
cd build_fpga && qsub-synth
cd $(FPGA_BUILD_DIR) && qsub-synth
setup-ase: build_ase/Makefile
setup-ase: $(ASE_BUILD_DIR)/Makefile
setup-fpga: build_fpga/build/dcp.qpf
setup-fpga: $(FPGA_BUILD_DIR)/build/dcp.qpf
build_ase/Makefile:
afu_sim_setup --s sources.txt build_ase
$(ASE_BUILD_DIR)/Makefile:
afu_sim_setup --s sources.txt $(ASE_BUILD_DIR)
build_fpga/build/dcp.qpf:
afu_synth_setup -s sources.txt build_fpga
$(FPGA_BUILD_DIR)/build/dcp.qpf:
afu_synth_setup -s sources.txt $(FPGA_BUILD_DIR)
run-ase:
cd build_ase && make sim
cd $(ASE_BUILD_DIR) && make sim
wave:
vsim -view build_ase/work/vsim.wlf -do wave.do
vsim -view $(ASE_BUILD_DIR)/work/vsim.wlf -do wave.do
run-fpga:
# TODO
clean-ase:
rm -rf build_ase
rm -rf $(ASE_BUILD_DIR)
clean-fpga:
rm -rf build_fpga
rm -rf $(FPGA_BUILD_DIR)

2
driver/hw/vortex_afu.sv
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@@ -246,6 +246,7 @@ begin
STATE_RUN: begin
if (vx_ebreak)
begin
// TODO: Add delay stage before returning to IDLE
state <= STATE_IDLE;
end
end
@@ -253,6 +254,7 @@ begin
STATE_SNOOP1: begin
if (vx_snoop_delay >= VX_SNOOPING_DELAY)
begin
// TODO: Allow both RUN and SNOOP states to use the AVS bus
state <= STATE_SNOOP2;
end
end

12
driver/hw/wave.do
View File

@@ -27,12 +27,16 @@ add wave -noupdate -label avs_raq_full /ase_top/ase_top_generic/platform_shim_cc
add wave -noupdate -label avs_rdq_full /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_rdq_full
add wave -noupdate -label avs_raq_empty /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_raq_empty
add wave -noupdate -label avs_rdq_empty /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_rdq_empty
add wave -noupdate -label vx_reset /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/reset
add wave -noupdate -label vx_dram_req_read /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_dram_req_read
add wave -noupdate -label vx_dram_req_write /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_dram_req_write
add wave -noupdate -label vx_dram_req_delay /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_dram_req_delay
add wave -noupdate -label vx_dram_req_read /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_dram_req_read
add wave -noupdate -label vx_reset /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/reset
add wave -noupdate -label vx_dram_req_addr -radix hexadecimal /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_dram_req_addr
add wave -noupdate -label vx_draw_req_data -radix hexadecimal /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_dram_req_data
add wave -noupdate -label out_dram_fill_rsp /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/out_dram_fill_rsp
add wave -noupdate -label out_dram_fill_accept /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/out_dram_fill_accept
add wave -noupdate -label vx_draw_fill_rsp_data -radix hexadecimal /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_dram_fill_rsp_data
add wave -noupdate -label vx_dram_fill_rsp_addr -radix hexadecimal /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_dram_fill_rsp_addr
add wave -noupdate -label llc_snp_req /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/llc_snp_req
add wave -noupdate -label llc_snp_req_delay /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/llc_snp_req_delay
add wave -noupdate -label out_break /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/out_ebreak
@@ -45,7 +49,7 @@ add wave -noupdate -label warp_stalled {/ase_top/ase_top_generic/platform_shim_c
add wave -noupdate -label warp_lock {/ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/genblk1/Vortex_Cluster/genblk1[0]/vortex_core/vx_front_end/vx_fetch/warp_scheduler/warp_lock}
add wave -noupdate -label use_active {/ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/genblk1/Vortex_Cluster/genblk1[0]/vortex_core/vx_front_end/vx_fetch/warp_scheduler/use_active}
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 2} {66234495 ps} 0}
WaveRestoreCursors {{Cursor 2} {620643200 ps} 0}
quietly wave cursor active 1
configure wave -namecolwidth 195
configure wave -valuecolwidth 100
@@ -61,4 +65,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {66041656 ps} {66406344 ps}
WaveRestoreZoom {620460856 ps} {620825544 ps}

2
driver/tests/basic/Makefile
View File

@@ -18,7 +18,7 @@ run-fpga: $(PROJECT)
LD_LIBRARY_PATH=../../sw/opae:$(LD_LIBRARY_PATH) ./$(PROJECT)
run-ase: $(PROJECT)
ASE_LOG=0 LD_LIBRARY_PATH=../../sw/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) -t 1
ASE_LOG=0 LD_LIBRARY_PATH=../../sw/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT)
run-rtlsim: $(PROJECT)
LD_LIBRARY_PATH=../../sw/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT)

81
driver/tests/basic/basic.cpp
View File

@@ -27,11 +27,11 @@ uint64_t shuffle(int i, uint64_t value) {
return (value << i) | (value & ((1 << i)-1));;
}
int run_test_0(vx_buffer_h sbuf,
vx_buffer_h dbuf,
uint32_t address,
uint64_t value,
int num_blocks) {
int run_memcpy_test(vx_buffer_h sbuf,
vx_buffer_h dbuf,
uint32_t address,
uint64_t value,
int num_blocks) {
int ret;
int errors = 0;
@@ -73,7 +73,7 @@ int run_test_0(vx_buffer_h sbuf,
return 0;
}
int run_test_1(vx_device_h device, const char* program) {
int run_riscv_test(vx_device_h device, const char* program) {
int ret;
// upload program
@@ -100,6 +100,40 @@ int run_test_1(vx_device_h device, const char* program) {
return 0;
}
int run_snoop_test(vx_device_h device) {
int ret;
// upload program
std::cout << "upload program" << std::endl;
ret = vx_upload_kernel_file(device, "rv32ui-p-lw.bin");
if (ret != 0) {
return ret;
}
// start device
std::cout << "start device" << std::endl;
ret = vx_start(device);
if (ret != 0) {
return ret;
}
// wait for completion
std::cout << "wait for completion" << std::endl;
ret = vx_ready_wait(device, -1);
if (ret != 0) {
return ret;
}
// send snooping request
std::cout << "flush the caches" << std::endl;
ret = vx_flush_caches(device, 0x80002000, 64);
if (ret != 0) {
return ret;
}
return 0;
}
vx_device_h device = nullptr;
vx_buffer_h sbuf = nullptr;
vx_buffer_h dbuf = nullptr;
@@ -147,27 +181,15 @@ int main(int argc, char *argv[]) {
// run tests
if (0 == test || -1 == test) {
std::cout << "run test suite 0" << std::endl;
std::cout << "run memcpy test" << std::endl;
ret = run_test_0(sbuf, dbuf, 0x10000000, 0x0badf00d00ff00ff, 1);
ret = run_memcpy_test(sbuf, dbuf, 0x10000000, 0x0badf00d00ff00ff, 1);
if (ret != 0) {
cleanup();
return ret;
}
ret = run_test_0(sbuf, dbuf, 0x10000000, 0x0badf00d00ff00ff, 2);
if (ret != 0) {
cleanup();
return ret;
}
ret = run_test_0(sbuf, dbuf, 0x20000000, 0xff00ff00ff00ff00, 4);
if (ret != 0) {
cleanup();
return ret;
}
ret = run_test_0(sbuf, dbuf, 0x20000000, 0x0badf00d40ff40ff, 8);
ret = run_memcpy_test(sbuf, dbuf, 0x20000000, 0x0badf00d40ff40ff, 8);
if (ret != 0) {
cleanup();
return ret;
@@ -175,8 +197,8 @@ int main(int argc, char *argv[]) {
}
if (1 == test || -1 == test) {
std::cout << "run test suite 1" << std::endl;
ret = run_test_1(device, "rv32ui-p-lw.bin");
std::cout << "run riscv-lw test" << std::endl;
ret = run_riscv_test(device, "rv32ui-p-lw.bin");
if (ret != 0) {
cleanup();
return ret;
@@ -184,8 +206,17 @@ int main(int argc, char *argv[]) {
}
if (2 == test || -1 == test) {
std::cout << "run test suite 1" << std::endl;
ret = run_test_1(device, "rv32ui-p-sw.bin");
std::cout << "run riscv-sw test" << std::endl;
ret = run_riscv_test(device, "rv32ui-p-sw.bin");
if (ret != 0) {
cleanup();
return ret;
}
}
if (3 == test || -1 == test) {
std::cout << "run snoop test" << std::endl;
ret = run_snoop_test(device);
if (ret != 0) {
cleanup();
return ret;

2
driver/tests/demo/Makefile
View File

@@ -46,7 +46,7 @@ run-fpga: $(PROJECT)
LD_LIBRARY_PATH=../../sw/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) -f kernel.bin -n 16
run-ase: $(PROJECT)
ASE_LOG=0 LD_LIBRARY_PATH=../../sw/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) -f kernel.bin -n 16
ASE_LOG=0 LD_LIBRARY_PATH=../../sw/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) -f kernel.bin -n 1
run-rtlsim: $(PROJECT)
LD_LIBRARY_PATH=../../sw/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) -f kernel.bin -n 16

7
rtl/VX_cache/VX_cache_dram_req_arb.v
View File

@@ -82,6 +82,9 @@ module VX_cache_dram_req_arb
wire pref_pop;
wire pref_valid;
wire[31:0] pref_addr;
wire dwb_valid;
wire dfqq_req;
assign pref_pop = !dwb_valid && !dfqq_req && !dram_req_delay && pref_valid;
VX_prefetcher #(
@@ -105,10 +108,8 @@ module VX_cache_dram_req_arb
);
wire dfqq_req;
wire[31:0] dfqq_req_addr;
wire dfqq_empty;
wire dwb_valid;
wire dfqq_empty;
wire dfqq_pop = !dwb_valid && dfqq_req && !dram_req_delay; // If no dwb, and dfqq has valids, then pop
wire dfqq_push = (|per_bank_dram_fill_req);