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Blaise Tine
2020-04-21 12:32:46 -07:00
parent f53256f854 43d8922f64
commit 24c81c4a3a
3 changed files with 4 additions and 5 deletions
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6
hw/rtl/VX_csr_data.v
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@@ -78,7 +78,7 @@ module VX_csr_data (
assign read_csr_data = read_cycle ? cycle[31:0] :
read_cycleh ? cycle[63:32] :
read_instret ? instret[31:0] :
read_instreth ? instret[63:32] :
{{20{1'b0}}, csr[read_addr]};
read_instret ? instret[31:0] :
read_instreth ? instret[63:32] :
{{20{1'b0}}, csr[read_addr]};
endmodule : VX_csr_data

1
hw/rtl/VX_scheduler.v
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@@ -50,7 +50,6 @@ module VX_scheduler (
integer i, w;
always @(posedge clk) begin
if (reset) begin
for (w = 0; w < `NUM_WARPS; w=w+1) begin
for (i = 0; i < 32; i = i + 1) begin

2
hw/rtl/cache/VX_cache_req_queue.v vendored
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@@ -173,7 +173,7 @@ module VX_cache_req_queue #(
always @(posedge clk) begin
if (reset) begin
use_per_valids <= 0;
use_per_valids <= 0;
use_per_addr <= 0;
use_per_writedata <= 0;
use_per_rd <= 0;