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Blaise Tine
2020-04-21 12:32:46 -07:00
parent f53256f854 43d8922f64
commit 24c81c4a3a
3 changed files with 4 additions and 5 deletions
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hw/rtl/VX_scheduler.v
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@@ -50,7 +50,6 @@ module VX_scheduler (
integer i, w; integer i, w;
always @(posedge clk) begin always @(posedge clk) begin
if (reset) begin if (reset) begin
for (w = 0; w < `NUM_WARPS; w=w+1) begin for (w = 0; w < `NUM_WARPS; w=w+1) begin
for (i = 0; i < 32; i = i + 1) begin for (i = 0; i < 32; i = i + 1) begin