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LKG Build (reset network update -fmax=236 mhz 4c)

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This commit is contained in:
Blaise Tine
2021-08-23 01:59:22 -07:00
parent 6caf674163
commit 2a27bfbfd5
11 changed files with 75 additions and 43 deletions
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4
hw/rtl/VX_cluster.v
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@@ -143,6 +143,8 @@ module VX_cluster #(
end else begin end else begin
`RESET_RELAY (mem_arb_reset);
VX_mem_arb #( VX_mem_arb #(
.NUM_REQS (`NUM_CORES), .NUM_REQS (`NUM_CORES),
.DATA_WIDTH (`L2MEM_DATA_WIDTH), .DATA_WIDTH (`L2MEM_DATA_WIDTH),
@@ -153,7 +155,7 @@ module VX_cluster #(
.BUFFERED_RSP (1) .BUFFERED_RSP (1)
) mem_arb ( ) mem_arb (
.clk (clk), .clk (clk),
.reset (reset), .reset (mem_arb_reset),
// Core request // Core request
.req_valid_in (per_core_mem_req_valid), .req_valid_in (per_core_mem_req_valid),

10
hw/rtl/VX_issue.v
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@@ -30,11 +30,15 @@ module VX_issue #(
wire scoreboard_delay; wire scoreboard_delay;
`RESET_RELAY (ibuf_reset);
`RESET_RELAY (gpr_reset);
`RESET_RELAY (demux_reset);
VX_ibuffer #( VX_ibuffer #(
.CORE_ID(CORE_ID) .CORE_ID(CORE_ID)
) ibuffer ( ) ibuffer (
.clk (clk), .clk (clk),
.reset (reset), .reset (ibuf_reset),
.decode_if (decode_if), .decode_if (decode_if),
.ibuffer_if (ibuffer_if) .ibuffer_if (ibuffer_if)
); );
@@ -58,7 +62,7 @@ module VX_issue #(
.CORE_ID(CORE_ID) .CORE_ID(CORE_ID)
) gpr_stage ( ) gpr_stage (
.clk (clk), .clk (clk),
.reset (reset), .reset (gpr_reset),
.writeback_if (writeback_if), .writeback_if (writeback_if),
.gpr_req_if (gpr_req_if), .gpr_req_if (gpr_req_if),
.gpr_rsp_if (gpr_rsp_if) .gpr_rsp_if (gpr_rsp_if)
@@ -80,7 +84,7 @@ module VX_issue #(
VX_instr_demux instr_demux ( VX_instr_demux instr_demux (
.clk (clk), .clk (clk),
.reset (reset), .reset (demux_reset),
.ibuffer_if (execute_if), .ibuffer_if (execute_if),
.gpr_rsp_if (gpr_rsp_if), .gpr_rsp_if (gpr_rsp_if),
.alu_req_if (alu_req_if), .alu_req_if (alu_req_if),

10
hw/rtl/VX_mem_unit.v
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@@ -65,6 +65,7 @@ module VX_mem_unit # (
`RESET_RELAY (icache_reset); `RESET_RELAY (icache_reset);
`RESET_RELAY (dcache_reset); `RESET_RELAY (dcache_reset);
`RESET_RELAY (mem_arb_reset);
VX_cache #( VX_cache #(
.CACHE_ID (`ICACHE_ID), .CACHE_ID (`ICACHE_ID),
@@ -197,6 +198,9 @@ module VX_mem_unit # (
.TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE) .TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE)
) smem_rsp_if(); ) smem_rsp_if();
`RESET_RELAY (smem_arb_reset);
`RESET_RELAY (smem_reset);
VX_smem_arb #( VX_smem_arb #(
.NUM_REQS (2), .NUM_REQS (2),
.LANES (`NUM_THREADS), .LANES (`NUM_THREADS),
@@ -207,7 +211,7 @@ module VX_mem_unit # (
.BUFFERED_RSP (1) .BUFFERED_RSP (1)
) smem_arb ( ) smem_arb (
.clk (clk), .clk (clk),
.reset (reset), .reset (smem_arb_reset),
// input request // input request
.req_valid_in (dcache_req_if.valid), .req_valid_in (dcache_req_if.valid),
@@ -242,8 +246,6 @@ module VX_mem_unit # (
.rsp_ready_out (dcache_rsp_if.ready) .rsp_ready_out (dcache_rsp_if.ready)
); );
`RESET_RELAY (smem_reset);
VX_shared_mem #( VX_shared_mem #(
.CACHE_ID (`SCACHE_ID), .CACHE_ID (`SCACHE_ID),
.CACHE_SIZE (`SMEM_SIZE), .CACHE_SIZE (`SMEM_SIZE),
@@ -312,7 +314,7 @@ module VX_mem_unit # (
.BUFFERED_RSP (2) .BUFFERED_RSP (2)
) mem_arb ( ) mem_arb (
.clk (clk), .clk (clk),
.reset (reset), .reset (mem_arb_reset),
// Source request // Source request
.req_valid_in ({dcache_mem_req_if.valid, icache_mem_req_if.valid}), .req_valid_in ({dcache_mem_req_if.valid, icache_mem_req_if.valid}),

1
hw/rtl/VX_platform.vh
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@@ -74,6 +74,7 @@
`define USE_FAST_BRAM (* ramstyle = "MLAB, no_rw_check" *) `define USE_FAST_BRAM (* ramstyle = "MLAB, no_rw_check" *)
`define NO_RW_RAM_CHECK (* altera_attribute = "-name add_pass_through_logic_to_inferred_rams off" *) `define NO_RW_RAM_CHECK (* altera_attribute = "-name add_pass_through_logic_to_inferred_rams off" *)
`define DISABLE_BRAM (* ramstyle = "logic" *) `define DISABLE_BRAM (* ramstyle = "logic" *)
`define PRESERVE_REG (* preserve *)
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////

2
hw/rtl/VX_warp_sched.v
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@@ -202,7 +202,7 @@ module VX_warp_sched #(
VX_priority_encoder #( VX_priority_encoder #(
.N (`NUM_WARPS) .N (`NUM_WARPS)
) rr_arbiter ( ) pri_enc (
.data_in (ready_warps), .data_in (ready_warps),
.index (schedule_wid), .index (schedule_wid),
.valid_out (schedule_valid), .valid_out (schedule_valid),

4
hw/rtl/Vortex.v
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@@ -141,6 +141,8 @@ module Vortex (
end else begin end else begin
`RESET_RELAY (mem_arb_reset);
VX_mem_arb #( VX_mem_arb #(
.NUM_REQS (`NUM_CLUSTERS), .NUM_REQS (`NUM_CLUSTERS),
.DATA_WIDTH (`L3MEM_DATA_WIDTH), .DATA_WIDTH (`L3MEM_DATA_WIDTH),
@@ -150,7 +152,7 @@ module Vortex (
.BUFFERED_RSP (1) .BUFFERED_RSP (1)
) mem_arb ( ) mem_arb (
.clk (clk), .clk (clk),
.reset (reset), .reset (mem_arb_reset),
// Core request // Core request
.req_valid_in (per_cluster_mem_req_valid), .req_valid_in (per_cluster_mem_req_valid),

18
hw/rtl/afu/vortex_afu.sv
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@@ -512,6 +512,8 @@ t_local_mem_data mem_rsp_data;
wire [AVS_REQ_TAGW:0] mem_rsp_tag; wire [AVS_REQ_TAGW:0] mem_rsp_tag;
wire mem_rsp_ready; wire mem_rsp_ready;
`RESET_RELAY (mem_arb_reset);
VX_mem_arb #( VX_mem_arb #(
.NUM_REQS (2), .NUM_REQS (2),
.DATA_WIDTH (LMEM_DATA_WIDTH), .DATA_WIDTH (LMEM_DATA_WIDTH),
@@ -522,7 +524,7 @@ VX_mem_arb #(
.TYPE ("X") .TYPE ("X")
) mem_arb ( ) mem_arb (
.clk (clk), .clk (clk),
.reset (reset), .reset (mem_arb_reset),
// Source request // Source request
.req_valid_in ({vx_mem_req_arb_valid, cci_mem_req_arb_valid}), .req_valid_in ({vx_mem_req_arb_valid, cci_mem_req_arb_valid}),
@@ -557,6 +559,8 @@ VX_mem_arb #(
//-- //--
`RESET_RELAY (avs_wrapper_reset);
VX_avs_wrapper #( VX_avs_wrapper #(
.AVS_DATA_WIDTH (LMEM_DATA_WIDTH), .AVS_DATA_WIDTH (LMEM_DATA_WIDTH),
.AVS_ADDR_WIDTH (LMEM_ADDR_WIDTH), .AVS_ADDR_WIDTH (LMEM_ADDR_WIDTH),
@@ -566,7 +570,7 @@ VX_avs_wrapper #(
.RD_QUEUE_SIZE (AVS_RD_QUEUE_SIZE) .RD_QUEUE_SIZE (AVS_RD_QUEUE_SIZE)
) avs_wrapper ( ) avs_wrapper (
.clk (clk), .clk (clk),
.reset (reset), .reset (avs_wrapper_reset),
// Memory request // Memory request
.mem_req_valid (mem_req_valid), .mem_req_valid (mem_req_valid),
@@ -724,13 +728,15 @@ always @(posedge clk) begin
end end
end end
`RESET_RELAY (cci_rdq_reset);
VX_fifo_queue #( VX_fifo_queue #(
.DATAW (CCI_RD_QUEUE_DATAW), .DATAW (CCI_RD_QUEUE_DATAW),
.SIZE (CCI_RD_QUEUE_SIZE), .SIZE (CCI_RD_QUEUE_SIZE),
.OUTPUT_REG (1) .OUTPUT_REG (1)
) cci_rd_req_queue ( ) cci_rd_req_queue (
.clk (clk), .clk (clk),
.reset (reset), .reset (cci_rdq_reset),
.push (cci_rdq_push), .push (cci_rdq_push),
.pop (cci_rdq_pop), .pop (cci_rdq_pop),
.data_in (cci_rdq_din), .data_in (cci_rdq_din),
@@ -878,7 +884,7 @@ Vortex #() vortex (
`SCOPE_BIND_afu_vortex `SCOPE_BIND_afu_vortex
.clk (clk), .clk (clk),
.reset (reset | vx_reset), .reset (reset || vx_reset),
// Memory request // Memory request
.mem_req_valid (vx_mem_req_valid), .mem_req_valid (vx_mem_req_valid),
@@ -997,6 +1003,8 @@ VX_fifo_queue #(
wire scope_changed = `SCOPE_TRIGGER; wire scope_changed = `SCOPE_TRIGGER;
`RESET_RELAY (scope_reset);
VX_scope #( VX_scope #(
.DATAW ($bits({`SCOPE_DATA_LIST,`SCOPE_UPDATE_LIST})), .DATAW ($bits({`SCOPE_DATA_LIST,`SCOPE_UPDATE_LIST})),
.BUSW (64), .BUSW (64),
@@ -1004,7 +1012,7 @@ VX_scope #(
.UPDW ($bits({`SCOPE_UPDATE_LIST})) .UPDW ($bits({`SCOPE_UPDATE_LIST}))
) scope ( ) scope (
.clk (clk), .clk (clk),
.reset (reset), .reset (scope_reset),
.start (1'b0), .start (1'b0),
.stop (1'b0), .stop (1'b0),
.changed (scope_changed), .changed (scope_changed),

20
hw/rtl/cache/VX_cache.v vendored
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@@ -151,8 +151,8 @@ module VX_cache #(
.MEM_TAG_IN_WIDTH (MEM_TAG_IN_WIDTH), .MEM_TAG_IN_WIDTH (MEM_TAG_IN_WIDTH),
.MEM_TAG_OUT_WIDTH (MEM_TAG_WIDTH) .MEM_TAG_OUT_WIDTH (MEM_TAG_WIDTH)
) nc_bypass ( ) nc_bypass (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
// Core request in // Core request in
.core_req_valid_in (core_req_valid), .core_req_valid_in (core_req_valid),
@@ -252,13 +252,15 @@ module VX_cache #(
wire mrsq_out_valid, mrsq_out_ready; wire mrsq_out_valid, mrsq_out_ready;
`RESET_RELAY (mrsq_reset);
VX_elastic_buffer #( VX_elastic_buffer #(
.DATAW (MEM_TAG_IN_WIDTH + `CACHE_LINE_WIDTH), .DATAW (MEM_TAG_IN_WIDTH + `CACHE_LINE_WIDTH),
.SIZE (MRSQ_SIZE), .SIZE (MRSQ_SIZE),
.OUTPUT_REG (MRSQ_SIZE > 2) .OUTPUT_REG (MRSQ_SIZE > 2)
) mem_rsp_queue ( ) mem_rsp_queue (
.clk (clk), .clk (clk),
.reset (reset), .reset (mrsq_reset),
.ready_in (mem_rsp_ready_nc), .ready_in (mem_rsp_ready_nc),
.valid_in (mem_rsp_valid_nc), .valid_in (mem_rsp_valid_nc),
.data_in ({mem_rsp_tag_nc, mem_rsp_data_nc}), .data_in ({mem_rsp_tag_nc, mem_rsp_data_nc}),
@@ -274,13 +276,15 @@ module VX_cache #(
wire [`LINE_SELECT_BITS-1:0] flush_addr; wire [`LINE_SELECT_BITS-1:0] flush_addr;
wire flush_enable; wire flush_enable;
`RESET_RELAY (flush_reset);
VX_flush_ctrl #( VX_flush_ctrl #(
.CACHE_SIZE (CACHE_SIZE), .CACHE_SIZE (CACHE_SIZE),
.CACHE_LINE_SIZE (CACHE_LINE_SIZE), .CACHE_LINE_SIZE (CACHE_LINE_SIZE),
.NUM_BANKS (NUM_BANKS) .NUM_BANKS (NUM_BANKS)
) flush_ctrl ( ) flush_ctrl (
.clk (clk), .clk (clk),
.reset (reset), .reset (flush_reset),
.addr_out (flush_addr), .addr_out (flush_addr),
.valid_out (flush_enable) .valid_out (flush_enable)
); );
@@ -436,6 +440,8 @@ module VX_cache #(
assign curr_bank_mem_rsp_data = mem_rsp_data_qual; assign curr_bank_mem_rsp_data = mem_rsp_data_qual;
assign per_bank_mem_rsp_ready[i] = curr_bank_mem_rsp_ready; assign per_bank_mem_rsp_ready[i] = curr_bank_mem_rsp_ready;
`RESET_RELAY (bank_reset);
VX_bank #( VX_bank #(
.BANK_ID (i), .BANK_ID (i),
.CACHE_ID (CACHE_ID), .CACHE_ID (CACHE_ID),
@@ -457,7 +463,7 @@ module VX_cache #(
`SCOPE_BIND_VX_cache_bank(i) `SCOPE_BIND_VX_cache_bank(i)
.clk (clk), .clk (clk),
.reset (reset), .reset (bank_reset),
`ifdef PERF_ENABLE `ifdef PERF_ENABLE
.perf_read_misses (perf_read_miss_per_bank[i]), .perf_read_misses (perf_read_miss_per_bank[i]),
@@ -539,13 +545,15 @@ module VX_cache #(
wire [MSHR_ADDR_WIDTH-1:0] mem_req_id; wire [MSHR_ADDR_WIDTH-1:0] mem_req_id;
`RESET_RELAY (mreq_reset);
VX_stream_arbiter #( VX_stream_arbiter #(
.NUM_REQS (NUM_BANKS), .NUM_REQS (NUM_BANKS),
.DATAW (`MEM_ADDR_WIDTH + MSHR_ADDR_WIDTH + 1 + CACHE_LINE_SIZE + `CACHE_LINE_WIDTH), .DATAW (`MEM_ADDR_WIDTH + MSHR_ADDR_WIDTH + 1 + CACHE_LINE_SIZE + `CACHE_LINE_WIDTH),
.BUFFERED (1) .BUFFERED (1)
) mem_req_arb ( ) mem_req_arb (
.clk (clk), .clk (clk),
.reset (reset), .reset (mreq_reset),
.valid_in (per_bank_mem_req_valid), .valid_in (per_bank_mem_req_valid),
.data_in (data_in), .data_in (data_in),
.ready_in (per_bank_mem_req_ready), .ready_in (per_bank_mem_req_ready),

2
hw/rtl/libs/VX_onehot_encoder.v
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@@ -1,7 +1,7 @@
`include "VX_platform.vh" `include "VX_platform.vh"
// Fast encoder using parallel prefix computation // Fast encoder using parallel prefix computation
// Adapter from BaseJump STL: http://bjump.org/data_out.html // Adapted from BaseJump STL: http://bjump.org/data_out.html
`TRACING_OFF `TRACING_OFF
module VX_onehot_encoder #( module VX_onehot_encoder #(

31
hw/rtl/libs/VX_reset_relay.v
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@@ -1,26 +1,31 @@
`include "VX_platform.vh" `include "VX_platform.vh"
`TRACING_OFF
module VX_reset_relay #( module VX_reset_relay #(
parameter ASYNC = 0 parameter N = 1,
parameter DEPTH = 1
) ( ) (
input wire clk, input wire clk,
input wire reset, input wire reset,
output wire reset_o output wire [N-1:0] reset_o
); );
(* preserve *) reg reset_r;
if (ASYNC) begin if (DEPTH > 1) begin
always @(posedge clk or posedge reset) begin `PRESERVE_REG `DISABLE_BRAM reg [N-1:0] reset_r [DEPTH-1:0];
reset_r <= reset;
end
end else begin
always @(posedge clk) begin always @(posedge clk) begin
reset_r <= reset; for (integer i = DEPTH-1; i > 0; --i)
reset_r[i] <= reset_r[i-1];
reset_r[0] <= {N{reset}};
end end
assign reset_o = reset_r[DEPTH-1];
end else if (DEPTH == 1) begin
`PRESERVE_REG reg [N-1:0] reset_r;
always @(posedge clk) begin
reset_r <= {N{reset}};
end
assign reset_o = reset_r;
end else begin
`UNUSED_VAR (clk)
assign reset_o = {N{reset}};
end end
assign reset_o = reset_r;
endmodule endmodule
`TRACING_ON

12
hw/syn/opae/vortex_afu.qsf
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@@ -23,12 +23,12 @@ set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name USE_HIGH_SPEED_ADDER ON #set_global_assignment -name USE_HIGH_SPEED_ADDER ON
set_global_assignment -name MUX_RESTRUCTURE ON #set_global_assignment -name MUX_RESTRUCTURE ON
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON #set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "FORCE ALL TILES WITH FAILING TIMING PATHS TO HIGH SPEED" #set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "FORCE ALL TILES WITH FAILING TIMING PATHS TO HIGH SPEED"
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON #set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON #set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100