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Got queue_ll to work by modifying when to update bypass

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This commit is contained in:
felsabbagh3
2020-03-06 22:50:20 -08:00
parent abfd592fd2
commit 2c616d8201
5 changed files with 37 additions and 28 deletions
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10
rtl/VX_cache/VX_bank.v
View File

@@ -62,7 +62,7 @@ module VX_bank (
reg snrq_hazard_st0;
assign snrq_valid_st0 = !snrq_empty;
VX_generic_queue #(.DATAW(32), .SIZE(`SNRQ_SIZE)) snr_queue(
VX_generic_queue_ll #(.DATAW(32), .SIZE(`SNRQ_SIZE)) snr_queue(
.clk (clk),
.reset (reset),
.push (snp_req),
@@ -82,7 +82,7 @@ module VX_bank (
assign dram_fill_accept = !dfpq_full;
VX_generic_queue #(.DATAW(32+(`BANK_LINE_SIZE_WORDS*32)), .SIZE(`DFPQ_SIZE)) dfp_queue(
VX_generic_queue_ll #(.DATAW(32+(`BANK_LINE_SIZE_WORDS*32)), .SIZE(`DFPQ_SIZE)) dfp_queue(
.clk (clk),
.reset (reset),
.push (dram_fill_rsp),
@@ -199,7 +199,7 @@ module VX_bank (
assign dfpq_pop = !dfpq_empty && !stall_bank_pipe && !dfpq_hazard_st0;
assign mrvq_pop = !dfpq_pop && mrvq_valid_st0 && !stall_bank_pipe && !mrvq_hazard_st0;
assign reqq_pop = !mrvq_pop && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0] && !reqq_hazard_st0;
assign reqq_pop = !mrvq_pop && !reqq_empty && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0] && !reqq_hazard_st0;
assign snrq_pop = !reqq_pop && snrq_valid_st0 && !stall_bank_pipe && !snrq_hazard_st0;
@@ -385,7 +385,7 @@ module VX_bank (
wire cwbq_full;
wire cwbq_empty;
assign bank_wb_valid = !cwbq_empty;
VX_generic_queue #(.DATAW( `vx_clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1+1) + 32), .SIZE(`CWBQ_SIZE)) cwb_queue(
VX_generic_queue_ll #(.DATAW( `vx_clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1+1) + 32), .SIZE(`CWBQ_SIZE)) cwb_queue(
.clk (clk),
.reset (reset),
@@ -425,7 +425,7 @@ module VX_bank (
assign dram_fill_req_addr = addr_st2;
assign dram_wb_req = !dwbq_empty;
VX_generic_queue #(.DATAW( 1 + 32 + (`BANK_LINE_SIZE_WORDS * 32) + 1 + 1), .SIZE(`DWBQ_SIZE)) dwb_queue(
VX_generic_queue_ll #(.DATAW( 1 + 32 + (`BANK_LINE_SIZE_WORDS * 32) + 1 + 1), .SIZE(`DWBQ_SIZE)) dwb_queue(
.clk (clk),
.reset (reset),

13
rtl/VX_cache/VX_cache_dfq_queue.v
View File

@@ -28,24 +28,26 @@ module VX_cache_dfq_queue
wire[`NUMBER_BANKS-1:0] updated_bank_dram_fill_req;
wire o_empty;
wire use_empty = !(|use_per_bank_dram_fill_req);
wire out_empty = !(|out_per_bank_dram_fill_req);
wire out_empty = !(|out_per_bank_dram_fill_req) || o_empty;
wire push_qual = dfqq_push && !dfqq_full;
wire pop_qual = dfqq_pop && use_empty && !out_empty && !dfqq_empty;
VX_generic_queue #(.DATAW(`NUMBER_BANKS * (1+32)), .SIZE(`DFQQ_SIZE)) dfqq_queue(
wire pop_qual = dfqq_pop && use_empty && !out_empty;
VX_generic_queue_ll #(.DATAW(`NUMBER_BANKS * (1+32)), .SIZE(`DFQQ_SIZE)) dfqq_queue(
.clk (clk),
.reset (reset),
.push (push_qual),
.in_data ({per_bank_dram_fill_req, per_bank_dram_fill_req_addr}),
.pop (pop_qual),
.out_data({out_per_bank_dram_fill_req, out_per_bank_dram_fill_req_addr}),
.empty (dfqq_empty),
.empty (o_empty),
.full (dfqq_full)
);
assign qual_bank_dram_fill_req = use_empty ? out_per_bank_dram_fill_req : use_per_bank_dram_fill_req;
assign qual_bank_dram_fill_req_addr = use_empty ? out_per_bank_dram_fill_req_addr : use_per_bank_dram_fill_req_addr;
@@ -57,6 +59,7 @@ module VX_cache_dfq_queue
.found (qual_has_request)
);
assign dfqq_empty = !qual_has_request;
assign dfqq_req = qual_bank_dram_fill_req [qual_request_index];
assign dfqq_req_addr = qual_bank_dram_fill_req_addr[qual_request_index];

20
rtl/VX_cache/VX_cache_req_queue.v
View File

@@ -63,25 +63,27 @@ module VX_cache_req_queue (
wire[`NUMBER_REQUESTS-1:0] updated_valids;
wire o_empty;
wire use_empty = !(|use_per_valids);
wire out_empty = !(|out_per_valids);
wire out_empty = !(|out_per_valids) || o_empty;
wire push_qual = reqq_push && !reqq_full;
wire pop_qual = reqq_pop && use_empty && !out_empty && !reqq_empty;
wire pop_qual = reqq_pop && use_empty && !out_empty;
VX_generic_queue #(.DATAW( (`NUMBER_REQUESTS * (1+32+32)) + 5 + 2 + (`NW_M1+1) + 3 + 3 ), .SIZE(`REQQ_SIZE)) reqq_queue(
VX_generic_queue_ll #(.DATAW( (`NUMBER_REQUESTS * (1+32+32)) + 5 + 2 + (`NW_M1+1) + 3 + 3 ), .SIZE(`REQQ_SIZE)) reqq_queue(
.clk (clk),
.reset (reset),
.push (push_qual),
.in_data ({bank_valids , bank_addr , bank_writedata , bank_rd , bank_wb , bank_warp_num , bank_mem_read , bank_mem_write}),
.pop (pop_qual),
.out_data({out_per_valids, out_per_addr, out_per_writedata, out_per_rd, out_per_wb, out_per_warp_num, out_per_mem_read, out_per_mem_write}),
.empty (reqq_empty),
.empty (o_empty),
.full (reqq_full)
);
wire[`NUMBER_REQUESTS-1:0] real_out_per_valids = out_per_valids & {`NUMBER_REQUESTS{~reqq_empty}};
wire[`NUMBER_REQUESTS-1:0] real_out_per_valids = out_per_valids & {`NUMBER_REQUESTS{~out_empty}};
assign qual_valids = use_empty ? real_out_per_valids : out_empty ? 0 : use_per_valids;
assign qual_addr = use_empty ? out_per_addr : use_per_addr;
@@ -100,6 +102,7 @@ module VX_cache_req_queue (
.found (qual_has_request)
);
assign reqq_empty = !qual_has_request;
assign reqq_req_st0 = qual_has_request;
assign reqq_req_tid_st0 = qual_request_index;
assign reqq_req_addr_st0 = qual_addr [qual_request_index];
@@ -132,9 +135,10 @@ module VX_cache_req_queue (
use_per_warp_num <= qual_warp_num;
use_per_mem_read <= qual_mem_read;
use_per_mem_write <= qual_mem_write;
end else if (reqq_pop) begin
use_per_valids[qual_request_index] <= updated_valids;
end
end
// else if (reqq_pop) begin
// use_per_valids[qual_request_index] <= updated_valids;
// end
end
end

16
rtl/VX_cache/VX_tag_data_access.v
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@@ -105,11 +105,11 @@ module VX_tag_data_access (
wire[`OFFSET_SIZE_RNG] byte_select = writeaddr_st1e[`OFFSET_ADDR_RNG];
wire[`WORD_SELECT_SIZE_RNG] block_offset = writeaddr_st1e[`WORD_SELECT_ADDR_RNG];
wire lw = (mem_read_st1e == `LW_MEM_READ);
wire lb = (mem_read_st1e == `LB_MEM_READ);
wire lh = (mem_read_st1e == `LH_MEM_READ);
wire lhu = (mem_read_st1e == `LHU_MEM_READ);
wire lbu = (mem_read_st1e == `LBU_MEM_READ);
wire lw = valid_req_st1e && (mem_read_st1e == `LW_MEM_READ);
wire lb = valid_req_st1e && (mem_read_st1e == `LB_MEM_READ);
wire lh = valid_req_st1e && (mem_read_st1e == `LH_MEM_READ);
wire lhu = valid_req_st1e && (mem_read_st1e == `LHU_MEM_READ);
wire lbu = valid_req_st1e && (mem_read_st1e == `LBU_MEM_READ);
wire b0 = (byte_select == 0);
wire b1 = (byte_select == 1);
@@ -160,9 +160,9 @@ module VX_tag_data_access (
/////////////////////// STORE LOGIC ///////////////////
wire sw = (mem_write_st1e == `SW_MEM_WRITE);
wire sb = (mem_write_st1e == `SB_MEM_WRITE);
wire sh = (mem_write_st1e == `SH_MEM_WRITE);
wire sw = valid_req_st1e && (mem_write_st1e == `SW_MEM_WRITE);
wire sb = valid_req_st1e && (mem_write_st1e == `SB_MEM_WRITE);
wire sh = valid_req_st1e && (mem_write_st1e == `SH_MEM_WRITE);
wire[3:0] sb_mask = (b0 ? 4'b0001 : (b1 ? 4'b0010 : (b2 ? 4'b0100 : 4'b1000)));
wire[3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100);

6
rtl/VX_generic_queue_ll.v
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@@ -92,8 +92,10 @@ module VX_generic_queue_ll
end
end
bypass_r <= writing && (empty_r || (1 == size_r && reading));
curr_r <= in_data;
if (!(!reading && bypass_r)) begin
bypass_r <= writing && (empty_r || (1 == size_r && reading));
curr_r <= in_data;
end
head_r <= data[reading ? rd_next_ptr_r : rd_ptr_r];
end
end