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cache refactoring - phase 3 - added dedicated pipeline stage for tag access

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This commit is contained in:
Blaise Tine
2020-11-04 03:21:30 -08:00
parent cd8ce20bd6
commit 4c6a74fa87
11 changed files with 545 additions and 339 deletions
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2
hw/rtl/VX_alu_unit.v
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@@ -31,7 +31,7 @@ module VX_alu_unit #(
wire [`NUM_THREADS-1:0][31:0] alu_in1_PC = alu_req_if.rs1_is_PC ? {`NUM_THREADS{alu_req_if.PC}} : alu_in1;
wire [`NUM_THREADS-1:0][31:0] alu_in2_imm = alu_req_if.rs2_is_imm ? {`NUM_THREADS{alu_req_if.imm}} : alu_in2;
wire [`NUM_THREADS-1:0][31:0] alu_in2_less = (alu_req_if.rs2_is_imm && ~is_br_op) ? {`NUM_THREADS{alu_req_if.imm}} : alu_in2;
wire [`NUM_THREADS-1:0][31:0] alu_in2_less = (alu_req_if.rs2_is_imm && !is_br_op) ? {`NUM_THREADS{alu_req_if.imm}} : alu_in2;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
always @(*) begin

2
hw/rtl/VX_decode.v
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@@ -295,7 +295,7 @@ module VX_decode #(
wire use_rs1 = is_fpu
|| is_gpu
|| ((is_jalr || is_btype || is_ltype || is_stype || is_itype || is_rtype || ~is_csr_imm || is_gpu) && (rs1 != 0));
|| ((is_jalr || is_btype || is_ltype || is_stype || is_itype || is_rtype || !is_csr_imm || is_gpu) && (rs1 != 0));
wire use_rs2 = (is_fpu && ~(is_fl || (fpu_op == `FPU_SQRT) || is_fcvti || is_fcvtf || is_fmvw_clss || is_fmvx))
|| (is_gpu && (gpu_op == `GPU_BAR || gpu_op == `GPU_WSPAWN))

337
hw/rtl/cache/VX_bank.v vendored
View File

@@ -122,6 +122,14 @@ module VX_bank #(
wire[WORD_SIZE-1:0] debug_byteen_st2;
wire[`REQS_BITS-1:0] debug_tid_st2;
wire[`UP(CORE_TAG_ID_BITS)-1:0] debug_tagid_st2;
wire[31:0] debug_pc_st3;
wire[`NR_BITS-1:0] debug_rd_st3;
wire[`NW_BITS-1:0] debug_wid_st3;
wire debug_rw_st3;
wire[WORD_SIZE-1:0] debug_byteen_st3;
wire[`REQS_BITS-1:0] debug_tid_st3;
wire[`UP(CORE_TAG_ID_BITS)-1:0] debug_tagid_st3;
/* verilator lint_on UNUSED */
`endif
@@ -245,21 +253,14 @@ module VX_bank #(
wire msrq_is_snp_st0;
wire msrq_snp_invalidate_st0;
wire msrq_pending_hazard_st1;
wire[`REQS_BITS-1:0] miss_add_tid;
wire[`REQ_TAG_WIDTH-1:0] miss_add_tag;
wire miss_add_rw;
wire[WORD_SIZE-1:0] miss_add_byteen;
wire[`LINE_ADDR_WIDTH-1:0] addr_st2;
wire is_msrq_miss_st2;
wire is_msrq_miss_st3;
wire msrq_push_stall;
wire cwbq_push_stall;
wire dwbq_push_stall;
wire snpq_push_stall;
wire stall_bank_pipe;
wire pipeline_stall;
wire is_fill_st1;
@@ -269,11 +270,11 @@ module VX_bank #(
wire reqq_pop_unqual = !msrq_pop_unqual && !dfpq_pop_unqual && !reqq_empty && !msrq_almfull;
wire snrq_pop_unqual = !msrq_pop_unqual && !dfpq_pop_unqual && !reqq_pop_unqual && !snrq_empty && !msrq_almfull;
assign msrq_pop = msrq_pop_unqual && !stall_bank_pipe
&& !is_msrq_miss_st2; // stop if previous request was a miss
assign dfpq_pop = dfpq_pop_unqual && !stall_bank_pipe;
assign reqq_pop = reqq_pop_unqual && !stall_bank_pipe;
assign snrq_pop = snrq_pop_unqual && !stall_bank_pipe;
assign msrq_pop = msrq_pop_unqual && !pipeline_stall
&& !(is_msrq_miss_st2 || is_msrq_miss_st3); // stop if previous request was a miss
assign dfpq_pop = dfpq_pop_unqual && !pipeline_stall;
assign reqq_pop = reqq_pop_unqual && !pipeline_stall;
assign snrq_pop = snrq_pop_unqual && !pipeline_stall;
wire is_fill_st0;
wire valid_st0;
@@ -298,6 +299,7 @@ module VX_bank #(
wire snp_invalidate_st1;
wire is_msrq_st1;
wire msrq_pending_hazard_st1;
wire[`LINE_ADDR_WIDTH-1:0] addr_st2;
assign is_msrq_st0 = msrq_pop_unqual;
@@ -339,9 +341,9 @@ module VX_bank #(
reqq_pop_unqual ? reqq_req_writeword_st0 :
0;
// we have a miss in msrq or in stage 2 for the current address
// we have a miss in msrq or in stage 3 for the current address
wire msrq_pending_hazard_st0 = msrq_pending_hazard_unqual_st0
|| (miss_add_unqual && (addr_st2 == addr_st0));
|| ((miss_st3 || force_miss_st3) && (addr_st3 == addr_st0));
`ifdef DBG_CORE_REQ_INFO
if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin
@@ -354,7 +356,7 @@ module VX_bank #(
) pipe_reg0 (
.clk (clk),
.reset (reset),
.stall (stall_bank_pipe),
.stall (pipeline_stall),
.flush (1'b0),
.in ({is_msrq_st0, is_snp_st0, snp_invalidate_st0, msrq_pending_hazard_st0, valid_st0, addr_st0, wsel_st0, writeword_st0, inst_meta_st0, is_fill_st0, writedata_st0}),
.out ({is_msrq_st1, is_snp_st1, snp_invalidate_st1, msrq_pending_hazard_st1, valid_st1, addr_st1, wsel_st1, writeword_st1, inst_meta_st1, is_fill_st1, writedata_st1})
@@ -366,31 +368,34 @@ module VX_bank #(
end
`endif
wire[`WORD_WIDTH-1:0] readword_st1;
wire[`BANK_LINE_WIDTH-1:0] readdata_st1;
wire[`TAG_SELECT_BITS-1:0] readtag_st1;
wire writeen_st1;
wire writeen_st2;
wire miss_st1;
wire miss_st2;
wire miss_st3;
wire dirty_st1;
wire[BANK_LINE_SIZE-1:0] dirtyb_st1;
wire mem_rw_st1;
wire [WORD_SIZE-1:0] mem_byteen_st1;
wire force_miss_st2;
`DEBUG_BEGIN
wire [`REQ_TAG_WIDTH-1:0] tag_st1;
wire [`REQS_BITS-1:0] tid_st1;
`DEBUG_END
wire mem_rw_st1;
wire [WORD_SIZE-1:0] mem_byteen_st1;
wire miss_add_unqual;
`DEBUG_END
assign {tag_st1, mem_rw_st1, mem_byteen_st1, tid_st1} = inst_meta_st1;
// we have a miss in st2 for the current address
wire st2_pending_hazard_st1 = miss_add_unqual && (addr_st2 == addr_st1);
// we have a matching previous request that missed alreedy
wire st2_pending_hazard_st1 = (miss_st2 || force_miss_st2) && (addr_st2 == addr_st1);
wire st3_pending_hazard_st1 = (miss_st3 || force_miss_st3) && (addr_st3 == addr_st1);
// force miss to ensure commit order when a new request has pending previous requests to same block
// also force a miss for msrq requests when previous request in st2 got a miss
wire force_miss_st1 = (valid_st1 && !is_msrq_st1 && ~is_fill_st1 && (msrq_pending_hazard_st1 || st2_pending_hazard_st1))
// also force a miss for msrq requests when previous requests got a miss
wire force_miss_st1 = (valid_st1 && !is_msrq_st1 && !is_fill_st1
&& (msrq_pending_hazard_st1 || st2_pending_hazard_st1 || st3_pending_hazard_st1))
|| (valid_st1 && is_msrq_st1 && is_msrq_miss_st2);
VX_tag_data_access #(
VX_tag_access #(
.BANK_ID (BANK_ID),
.CACHE_ID (CACHE_ID),
.CORE_TAG_ID_BITS(CORE_TAG_ID_BITS),
@@ -400,12 +405,10 @@ module VX_bank #(
.WORD_SIZE (WORD_SIZE),
.DRAM_ENABLE (DRAM_ENABLE),
.WRITE_ENABLE (WRITE_ENABLE)
) tag_data_access (
) tag_access (
.clk (clk),
.reset (reset),
.stall (stall_bank_pipe),
`ifdef DBG_CORE_REQ_INFO
.debug_pc_st1 (debug_pc_st1),
.debug_rd_st1 (debug_rd_st1),
@@ -413,27 +416,22 @@ module VX_bank #(
.debug_tagid_st1(debug_tagid_st1),
`endif
.stall (pipeline_stall),
// Actual Read/Write
.valid_req_st1 (valid_st1),
.writefill_st1 (is_fill_st1),
.addr_st1 (addr_st1),
.wordsel_st1 (wsel_st1),
.writeword_st1 (writeword_st1),
.writedata_st1 (writedata_st1),
.mem_rw_st1 (mem_rw_st1),
.mem_byteen_st1 (mem_byteen_st1),
.is_snp_st1 (is_snp_st1 && !stall_bank_pipe),
.is_snp_st1 (is_snp_st1),
.snp_invalidate_st1(snp_invalidate_st1),
.force_miss_st1 (force_miss_st1),
// Read Data
.readword_st1 (readword_st1),
.readdata_st1 (readdata_st1),
.readtag_st1 (readtag_st1),
.miss_st1 (miss_st1),
.dirty_st1 (dirty_st1),
.dirtyb_st1 (dirtyb_st1)
.writeen_st1 (writeen_st1)
);
wire valid_st2;
@@ -441,6 +439,8 @@ module VX_bank #(
wire [`WORD_WIDTH-1:0] writeword_st2;
wire [`WORD_WIDTH-1:0] readword_st2;
wire [`BANK_LINE_WIDTH-1:0] readdata_st2;
wire [`BANK_LINE_WIDTH-1:0] writedata_st2;
wire [WORD_SIZE-1:0] mem_byteen_st2;
wire miss_st2;
wire dirty_st2;
wire [BANK_LINE_SIZE-1:0] dirtyb_st2;
@@ -453,14 +453,14 @@ module VX_bank #(
wire is_msrq_st2;
VX_generic_register #(
.N(1+ 1+ 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + `WORD_WIDTH + `BANK_LINE_WIDTH + `TAG_SELECT_BITS + 1 + 1 + BANK_LINE_SIZE + `REQ_INST_META_WIDTH)
.N(1 + 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + `TAG_SELECT_BITS + 1 + 1 + `BANK_LINE_WIDTH + WORD_SIZE + `REQ_INST_META_WIDTH)
) pipe_reg1 (
.clk (clk),
.reset (reset),
.stall (stall_bank_pipe),
.stall (pipeline_stall),
.flush (1'b0),
.in ({is_msrq_st1, force_miss_st1, is_snp_st1, snp_invalidate_st1, is_fill_st1, valid_st1, addr_st1, wsel_st1, writeword_st1, readword_st1, readdata_st1, readtag_st1, miss_st1, dirty_st1, dirtyb_st1, inst_meta_st1}),
.out ({is_msrq_st2, force_miss_st2, is_snp_st2, snp_invalidate_st2, is_fill_st2, valid_st2, addr_st2, wsel_st2, writeword_st2, readword_st2, readdata_st2, readtag_st2, miss_st2, dirty_st2, dirtyb_st2, inst_meta_st2})
.in ({is_msrq_st1, writeen_st1, force_miss_st1, is_snp_st1, snp_invalidate_st1, is_fill_st1, valid_st1, addr_st1, wsel_st1, writeword_st1, readtag_st1, miss_st1, dirty_st1, writedata_st1, mem_byteen_st1, inst_meta_st1}),
.out ({is_msrq_st2, writeen_st2, force_miss_st2, is_snp_st2, snp_invalidate_st2, is_fill_st2, valid_st2, addr_st2, wsel_st2, writeword_st2, readtag_st2, miss_st2, dirty_st2, writedata_st2, mem_byteen_st2, inst_meta_st2})
);
`ifdef DBG_CORE_REQ_INFO
@@ -469,10 +469,92 @@ module VX_bank #(
end
`endif
assign is_msrq_miss_st2 = (miss_st2 || force_miss_st2) && is_msrq_st2;
VX_data_access #(
.BANK_ID (BANK_ID),
.CACHE_ID (CACHE_ID),
.CORE_TAG_ID_BITS(CORE_TAG_ID_BITS),
.CACHE_SIZE (CACHE_SIZE),
.BANK_LINE_SIZE (BANK_LINE_SIZE),
.NUM_BANKS (NUM_BANKS),
.WORD_SIZE (WORD_SIZE),
.DRAM_ENABLE (DRAM_ENABLE),
.WRITE_ENABLE (WRITE_ENABLE)
) data_access (
.clk (clk),
.reset (reset),
`ifdef DBG_CORE_REQ_INFO
.debug_pc_st2 (debug_pc_st2),
.debug_rd_st2 (debug_rd_st2),
.debug_wid_st2 (debug_wid_st2),
.debug_tagid_st2(debug_tagid_st2),
`endif
.stall (pipeline_stall),
// Actual Read/Write
.valid_req_st2 (valid_st2),
.writeen_st2 (writeen_st2),
.writefill_st2 (is_fill_st2),
.addr_st2 (addr_st2),
.wordsel_st2 (wsel_st2),
.mem_byteen_st2 (mem_byteen_st2),
.writeword_st2 (writeword_st2),
.writedata_st2 (writedata_st2),
// Read Data
.readword_st2 (readword_st2),
.readdata_st2 (readdata_st2),
.dirtyb_st2 (dirtyb_st2)
);
wire valid_st3;
wire [`LINE_ADDR_WIDTH-1:0] addr_st3;
wire [`UP(`WORD_SELECT_WIDTH)-1:0] wsel_st3;
wire [`WORD_WIDTH-1:0] writeword_st3;
wire [`WORD_WIDTH-1:0] readword_st3;
wire [`BANK_LINE_WIDTH-1:0] readdata_st3;
wire miss_st3;
wire dirty_st3;
wire [BANK_LINE_SIZE-1:0] dirtyb_st3;
wire [`REQ_INST_META_WIDTH-1:0] inst_meta_st3;
wire [`TAG_SELECT_BITS-1:0] readtag_st3;
wire is_fill_st3;
wire is_snp_st3;
wire snp_invalidate_st3;
wire force_miss_st3;
wire is_msrq_st3;
VX_generic_register #(
.N(1+ 1+ 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + `WORD_WIDTH + `BANK_LINE_WIDTH + `TAG_SELECT_BITS + 1 + 1 + BANK_LINE_SIZE + `REQ_INST_META_WIDTH)
) pipe_reg2 (
.clk (clk),
.reset (reset),
.stall (pipeline_stall),
.flush (1'b0),
.in ({is_msrq_st2, force_miss_st2, is_snp_st2, snp_invalidate_st2, is_fill_st2, valid_st2, addr_st2, wsel_st2, writeword_st2, readword_st2, readdata_st2, readtag_st2, miss_st2, dirty_st2, dirtyb_st2, inst_meta_st2}),
.out ({is_msrq_st3, force_miss_st3, is_snp_st3, snp_invalidate_st3, is_fill_st3, valid_st3, addr_st3, wsel_st3, writeword_st3, readword_st3, readdata_st3, readtag_st3, miss_st3, dirty_st3, dirtyb_st3, inst_meta_st3})
);
`ifdef DBG_CORE_REQ_INFO
if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin
assign {debug_pc_st3, debug_rd_st3, debug_wid_st3, debug_tagid_st3, debug_rw_st3, debug_byteen_st3, debug_tid_st3} = inst_meta_st3;
end
`endif
assign is_msrq_miss_st3 = (miss_st3 || force_miss_st3) && is_msrq_st3;
// Enqueue to miss reserv if it's a valid miss
assign miss_add_unqual = miss_st2 || force_miss_st2;
assign msrq_push_stall = miss_add_unqual && msrq_full;
wire[`REQS_BITS-1:0] miss_add_tid;
wire[`REQ_TAG_WIDTH-1:0] miss_add_tag;
wire miss_add_rw;
wire[WORD_SIZE-1:0] miss_add_byteen;
wire miss_add_unqual = miss_st3 || force_miss_st3;
assign msrq_push_stall = (miss_st3 || force_miss_st3) && msrq_full;
wire miss_add = miss_add_unqual
&& !msrq_full
@@ -480,34 +562,26 @@ module VX_bank #(
&& !dwbq_push_stall
&& !snpq_push_stall;
assign {miss_add_tag, miss_add_rw, miss_add_byteen, miss_add_tid} = inst_meta_st2;
assign {miss_add_tag, miss_add_rw, miss_add_byteen, miss_add_tid} = inst_meta_st3;
// we have a recurrent msrq miss
assign is_msrq_miss_st2 = miss_add_unqual && is_msrq_st2;
// a matching incoming fill request to the block is in stage 0
wire incoming_st0_fill_st2 = is_fill_st0 && (addr_st2 == dfpq_addr_st0);
// a matching incoming fill request to the block is in stage 1
wire incoming_st1_fill_st2 = is_fill_st1 && (addr_st2 == addr_st1);
// a matching fill request is comming
wire incoming_st0_fill_st3 = 0 /*is_fill_st0 && (addr_st3 == dfpq_addr_st0)*/; // clock delay issue
wire incoming_st1_fill_st3 = is_fill_st1 && (addr_st3 == addr_st1);
wire incoming_st2_fill_st3 = is_fill_st2 && (addr_st3 == addr_st2);
wire incoming_fill = incoming_st2_fill_st3
|| incoming_st1_fill_st3
|| incoming_st0_fill_st3;
if (DRAM_ENABLE) begin
wire [`LINE_ADDR_WIDTH-1:0] miss_add_addr = addr_st2;
wire [`UP(`WORD_SELECT_WIDTH)-1:0] miss_add_wsel = wsel_st2;
wire [`WORD_WIDTH-1:0] miss_add_data = writeword_st2;
wire miss_add_is_snp = is_snp_st2;
wire miss_add_snp_invalidate = snp_invalidate_st2;
wire msrq_real_pop_st2 = valid_st2 && is_msrq_st2 && !miss_add_unqual && !stall_bank_pipe;
wire msrq_dequeue_st3 = valid_st3 && is_msrq_st3 && !miss_add_unqual && !pipeline_stall;
// mark msrq entry that match DRAM fill as 'ready'
wire update_ready_st0 = dfpq_pop;
// push missed requests as 'ready'
// if it didn't actually missed but had to abort because of pending requets in msrq
wire msrq_init_ready_state_st2 = !miss_st2
|| incoming_st0_fill_st2
|| incoming_st1_fill_st2;
// or if a matching fill request is coming
wire msrq_init_ready_state_st3 = !miss_st3 || incoming_fill;
VX_cache_miss_resrv #(
.BANK_ID (BANK_ID),
@@ -529,53 +603,52 @@ module VX_bank #(
.debug_rd_st0 (debug_rd_st0),
.debug_wid_st0 (debug_wid_st0),
.debug_tagid_st0(debug_tagid_st0),
.debug_pc_st2 (debug_pc_st2),
.debug_rd_st2 (debug_rd_st2),
.debug_wid_st2 (debug_wid_st2),
.debug_tagid_st2(debug_tagid_st2),
.debug_pc_st3 (debug_pc_st3),
.debug_rd_st3 (debug_rd_st3),
.debug_wid_st3 (debug_wid_st3),
.debug_tagid_st3(debug_tagid_st3),
`endif
// enqueue
.miss_add (miss_add),
.miss_add_addr (miss_add_addr),
.miss_add_wsel (miss_add_wsel),
.miss_add_data (miss_add_data),
.miss_add_tid (miss_add_tid),
.miss_add_tag (miss_add_tag),
.miss_add_rw (miss_add_rw),
.miss_add_byteen (miss_add_byteen),
.miss_add_is_snp (miss_add_is_snp),
.miss_add_snp_invalidate (miss_add_snp_invalidate),
.is_msrq_st2 (is_msrq_st2),
.init_ready_state_st2 (msrq_init_ready_state_st2),
.miss_resrv_full (msrq_full),
.miss_resrv_almfull (msrq_almfull),
.enqueue_st3 (miss_add),
.enqueue_addr_st3 (addr_st3),
.enqueue_wsel_st3 (wsel_st3),
.enqueue_data_st3 (writeword_st3),
.enqueue_tid_st3 (miss_add_tid),
.enqueue_tag_st3 (miss_add_tag),
.enqueue_rw_st3 (miss_add_rw),
.enqueue_byteen_st3 (miss_add_byteen),
.enqueue_is_snp_st3 (is_snp_st3),
.enqueue_snp_inv_st3 (snp_invalidate_st3),
.enqueue_msrq_st3 (is_msrq_st3),
.enqueue_ready_st3 (msrq_init_ready_state_st3),
.enqueue_full (msrq_full),
.enqueue_almfull (msrq_almfull),
// fill
.update_ready_st0 (update_ready_st0),
.addr_st0 (addr_st0),
.pending_hazard_st0 (msrq_pending_hazard_unqual_st0),
.update_ready_st0 (update_ready_st0),
.addr_st0 (addr_st0),
.pending_hazard_st0 (msrq_pending_hazard_unqual_st0),
// dequeue
.miss_resrv_schedule_st0 (msrq_pop),
.miss_resrv_valid_st0 (msrq_valid_st0),
.miss_resrv_addr_st0 (msrq_addr_st0),
.miss_resrv_wsel_st0 (msrq_wsel_st0),
.miss_resrv_data_st0 (msrq_writeword_st0),
.miss_resrv_tid_st0 (msrq_tid_st0),
.miss_resrv_tag_st0 (msrq_tag_st0),
.miss_resrv_rw_st0 (msrq_rw_st0),
.miss_resrv_byteen_st0 (msrq_byteen_st0),
.miss_resrv_is_snp_st0 (msrq_is_snp_st0),
.miss_resrv_snp_invalidate_st0 (msrq_snp_invalidate_st0),
.miss_resrv_pop_st2 (msrq_real_pop_st2)
.schedule_st0 (msrq_pop),
.dequeue_valid_st0 (msrq_valid_st0),
.dequeue_addr_st0 (msrq_addr_st0),
.dequeue_wsel_st0 (msrq_wsel_st0),
.dequeue_data_st0 (msrq_writeword_st0),
.dequeue_tid_st0 (msrq_tid_st0),
.dequeue_tag_st0 (msrq_tag_st0),
.dequeue_rw_st0 (msrq_rw_st0),
.dequeue_byteen_st0 (msrq_byteen_st0),
.dequeue_is_snp_st0 (msrq_is_snp_st0),
.dequeue_snp_inv_st0 (msrq_snp_invalidate_st0),
.dequeue_st3 (msrq_dequeue_st3)
);
end else begin
`UNUSED_VAR (miss_add)
`UNUSED_VAR (wsel_st2)
`UNUSED_VAR (writeword_st2)
`UNUSED_VAR (snp_invalidate_st2)
`UNUSED_VAR (wsel_st3)
`UNUSED_VAR (writeword_st3)
`UNUSED_VAR (snp_invalidate_st3)
`UNUSED_VAR (miss_add_byteen)
assign msrq_pending_hazard_unqual_st0 = 0;
assign msrq_full = 0;
@@ -596,7 +669,7 @@ module VX_bank #(
wire cwbq_empty, cwbq_full;
wire cwbq_push_unqual = valid_st2 && !is_fill_st2 && !is_snp_st2 && !miss_st2 && !force_miss_st2 && !miss_add_rw;
wire cwbq_push_unqual = valid_st3 && !is_fill_st3 && !is_snp_st3 && !miss_st3 && !force_miss_st3 && !miss_add_rw;
assign cwbq_push_stall = cwbq_push_unqual && cwbq_full;
wire cwbq_push = cwbq_push_unqual
@@ -609,7 +682,7 @@ module VX_bank #(
wire [`REQS_BITS-1:0] cwbq_tid = miss_add_tid;
wire [CORE_TAG_WIDTH-1:0] cwbq_tag = CORE_TAG_WIDTH'(miss_add_tag);
wire [`WORD_WIDTH-1:0] cwbq_data = readword_st2;
wire [`WORD_WIDTH-1:0] cwbq_data = readword_st3;
VX_generic_queue #(
.DATAW(`REQS_BITS + CORE_TAG_WIDTH + `WORD_WIDTH),
@@ -631,11 +704,9 @@ module VX_bank #(
// Enqueue DRAM request
wire dwbq_empty, dwbq_full;
wire incoming_fill = incoming_st0_fill_st2 || incoming_st1_fill_st2;
wire dwbq_is_dfl_in = valid_st2 && miss_st2 && !incoming_fill && (!force_miss_st2 || is_msrq_st2);
wire dwbq_is_dwb_in = valid_st2 && dirty_st2 && !force_miss_st2 && (is_fill_st2 || is_snp_st2);
wire dwbq_is_dfl_in = valid_st3 && miss_st3 && !incoming_fill && (!force_miss_st3 || is_msrq_st3);
wire dwbq_is_dwb_in = valid_st3 && dirty_st3 && !force_miss_st3 && (is_fill_st3 || is_snp_st3);
wire dwbq_push_unqual = dwbq_is_dfl_in || dwbq_is_dwb_in;
assign dwbq_push_stall = dwbq_push_unqual && dwbq_full;
@@ -650,8 +721,8 @@ module VX_bank #(
if (DRAM_ENABLE) begin
wire [`LINE_ADDR_WIDTH-1:0] dwbq_req_addr = dwbq_is_dwb_in ? {readtag_st2, addr_st2[`LINE_SELECT_BITS-1:0]} :
addr_st2;
wire [`LINE_ADDR_WIDTH-1:0] dwbq_req_addr = dwbq_is_dwb_in ? {readtag_st3, addr_st3[`LINE_SELECT_BITS-1:0]} :
addr_st3;
VX_generic_queue #(
.DATAW(1 + BANK_LINE_SIZE + `LINE_ADDR_WIDTH + `BANK_LINE_WIDTH),
@@ -661,7 +732,7 @@ module VX_bank #(
.reset (reset),
.push (dwbq_push),
.pop (dwbq_pop),
.data_in ({dwbq_is_dwb_in, dirtyb_st2, dwbq_req_addr, readdata_st2}),
.data_in ({dwbq_is_dwb_in, dirtyb_st3, dwbq_req_addr, readdata_st3}),
.data_out({dram_req_rw, dram_req_byteen, dram_req_addr, dram_req_data}),
.empty (dwbq_empty),
.full (dwbq_full),
@@ -670,9 +741,9 @@ module VX_bank #(
end else begin
`UNUSED_VAR (dwbq_push)
`UNUSED_VAR (dwbq_pop)
`UNUSED_VAR (readtag_st2)
`UNUSED_VAR (dirtyb_st2)
`UNUSED_VAR (readdata_st2)
`UNUSED_VAR (readtag_st3)
`UNUSED_VAR (dirtyb_st3)
`UNUSED_VAR (readdata_st3)
assign dwbq_empty = 1;
assign dwbq_full = 0;
assign dram_req_rw = 0;
@@ -688,7 +759,7 @@ module VX_bank #(
wire snpq_empty, snpq_full;
wire snpq_push_unqual = valid_st2 && is_snp_st2 && !force_miss_st2;
wire snpq_push_unqual = valid_st3 && is_snp_st3 && !force_miss_st3;
assign snpq_push_stall = snpq_push_unqual && snpq_full;
@@ -700,7 +771,7 @@ module VX_bank #(
wire snpq_pop = snp_rsp_valid && snp_rsp_ready;
wire [SNP_REQ_TAG_WIDTH-1:0] snpq_tag_st2 = SNP_REQ_TAG_WIDTH'(miss_add_tag);
wire [SNP_REQ_TAG_WIDTH-1:0] snpq_tag_st3 = SNP_REQ_TAG_WIDTH'(miss_add_tag);
if (FLUSH_ENABLE) begin
@@ -712,7 +783,7 @@ module VX_bank #(
.reset (reset),
.push (snpq_push),
.pop (snpq_pop),
.data_in (snpq_tag_st2),
.data_in (snpq_tag_st3),
.data_out(snp_rsp_tag),
.empty (snpq_empty),
.full (snpq_full),
@@ -721,7 +792,7 @@ module VX_bank #(
end else begin
`UNUSED_VAR (snpq_push)
`UNUSED_VAR (snpq_pop)
`UNUSED_VAR (snpq_tag_st2)
`UNUSED_VAR (snpq_tag_st3)
assign snpq_empty = 1;
assign snpq_full = 0;
assign snp_rsp_tag = 0;
@@ -732,30 +803,32 @@ module VX_bank #(
&& dwbq_empty; // ensure all writebacks are sent
// bank pipeline stall
assign stall_bank_pipe = msrq_push_stall
|| cwbq_push_stall
|| dwbq_push_stall
|| snpq_push_stall;
assign pipeline_stall = msrq_push_stall
|| cwbq_push_stall
|| dwbq_push_stall
|| snpq_push_stall;
`SCOPE_ASSIGN (valid_st0, valid_st0);
`SCOPE_ASSIGN (valid_st1, valid_st1);
`SCOPE_ASSIGN (valid_st, valid_st1);
`SCOPE_ASSIGN (valid_st2, valid_st2);
`SCOPE_ASSIGN (valid_st3, valid_st3);
`SCOPE_ASSIGN (is_msrq_st1, is_msrq_st1);
`SCOPE_ASSIGN (miss_st1, miss_st1);
`SCOPE_ASSIGN (dirty_st1, dirty_st1);
`SCOPE_ASSIGN (force_miss_st1, force_miss_st1);
`SCOPE_ASSIGN (stall_pipe, stall_bank_pipe);
`SCOPE_ASSIGN (stall_pipe, pipeline_stall);
`SCOPE_ASSIGN (addr_st0, `LINE_TO_BYTE_ADDR(addr_st0, BANK_ID));
`SCOPE_ASSIGN (addr_st1, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID));
`SCOPE_ASSIGN (addr_st2, `LINE_TO_BYTE_ADDR(addr_st2, BANK_ID));
`SCOPE_ASSIGN (addr_st3, `LINE_TO_BYTE_ADDR(addr_st3, BANK_ID));
`ifdef DBG_PRINT_CACHE_BANK
always @(posedge clk) begin
if (miss_st2 && (incoming_st0_fill_st2 || incoming_st1_fill_st2)) begin
$display("%t: incoming fill - addr=%0h, st0=%b, st1=%b", $time, `LINE_TO_BYTE_ADDR(addr_st2, BANK_ID), incoming_st0_fill_st2, incoming_st1_fill_st2);
assert(!is_msrq_st2);
if (miss_st3 && (incoming_st0_fill_st3 || incoming_st2_fill_st3)) begin
$display("%t: incoming fill - addr=%0h, st0=%b, st1=%b", $time, `LINE_TO_BYTE_ADDR(addr_st3, BANK_ID), incoming_st0_fill_st3, incoming_st2_fill_st3);
assert(!is_msrq_st3);
end
if ((|core_req_valid) && core_req_ready) begin
$display("%t: cache%0d:%0d core-req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(core_req_addr[0], BANK_ID), core_req_tag);
@@ -788,13 +861,13 @@ module VX_bank #(
$display("%t: cache%0d:%0d snrq-pop: addr=%0h tag=%0d", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st0, BANK_ID), snrq_tag_st0);
end
if (cwbq_push) begin
$display("%t: cache%0d:%0d cwbq-push: addr=%0h wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st2, BANK_ID), debug_wid_st2, debug_pc_st2);
$display("%t: cache%0d:%0d cwbq-push: addr=%0h wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st3, BANK_ID), debug_wid_st3, debug_pc_st3);
end
if (dwbq_push) begin
$display("%t: cache%0d:%0d dwbq-push: addr=%0h wid=%0d, PC=%0h, rw=%b", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st2, BANK_ID), debug_wid_st2, debug_pc_st2, dwbq_is_dwb_in);
$display("%t: cache%0d:%0d dwbq-push: addr=%0h wid=%0d, PC=%0h, rw=%b", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st3, BANK_ID), debug_wid_st3, debug_pc_st3, dwbq_is_dwb_in);
end
if (snpq_push) begin
$display("%t: cache%0d:%0d snpq-push: addr=%0h tag=%0d", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st2, BANK_ID), snpq_tag_st2);
$display("%t: cache%0d:%0d snpq-push: addr=%0h tag=%0d", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st3, BANK_ID), snpq_tag_st3);
end
end
`endif

128
hw/rtl/cache/VX_cache_miss_resrv.v vendored
View File

@@ -30,29 +30,28 @@ module VX_cache_miss_resrv #(
input wire[`NR_BITS-1:0] debug_rd_st0,
input wire[`NW_BITS-1:0] debug_wid_st0,
input wire[`UP(CORE_TAG_ID_BITS)-1:0] debug_tagid_st0,
input wire[31:0] debug_pc_st2,
input wire[`NR_BITS-1:0] debug_rd_st2,
input wire[`NW_BITS-1:0] debug_wid_st2,
input wire[`UP(CORE_TAG_ID_BITS)-1:0] debug_tagid_st2,
input wire[31:0] debug_pc_st3,
input wire[`NR_BITS-1:0] debug_rd_st3,
input wire[`NW_BITS-1:0] debug_wid_st3,
input wire[`UP(CORE_TAG_ID_BITS)-1:0] debug_tagid_st3,
`IGNORE_WARNINGS_END
`endif
// enqueue
input wire miss_add,
input wire[`LINE_ADDR_WIDTH-1:0] miss_add_addr,
input wire[`UP(`WORD_SELECT_WIDTH)-1:0] miss_add_wsel,
input wire[`WORD_WIDTH-1:0] miss_add_data,
input wire[`REQS_BITS-1:0] miss_add_tid,
input wire[`REQ_TAG_WIDTH-1:0] miss_add_tag,
input wire miss_add_rw,
input wire[WORD_SIZE-1:0] miss_add_byteen,
input wire miss_add_is_snp,
input wire miss_add_snp_invalidate,
input wire is_msrq_st2,
input wire init_ready_state_st2,
output wire miss_resrv_full,
output wire miss_resrv_almfull,
input wire enqueue_st3,
input wire[`LINE_ADDR_WIDTH-1:0] enqueue_addr_st3,
input wire[`UP(`WORD_SELECT_WIDTH)-1:0] enqueue_wsel_st3,
input wire[`WORD_WIDTH-1:0] enqueue_data_st3,
input wire[`REQS_BITS-1:0] enqueue_tid_st3,
input wire[`REQ_TAG_WIDTH-1:0] enqueue_tag_st3,
input wire enqueue_rw_st3,
input wire[WORD_SIZE-1:0] enqueue_byteen_st3,
input wire enqueue_is_snp_st3,
input wire enqueue_snp_inv_st3,
input wire enqueue_msrq_st3,
input wire enqueue_ready_st3,
output wire enqueue_full,
output wire enqueue_almfull,
// fill
input wire update_ready_st0,
@@ -60,20 +59,20 @@ module VX_cache_miss_resrv #(
output wire pending_hazard_st0,
// dequeue
input wire miss_resrv_schedule_st0,
output wire miss_resrv_valid_st0,
output wire[`LINE_ADDR_WIDTH-1:0] miss_resrv_addr_st0,
output wire[`UP(`WORD_SELECT_WIDTH)-1:0] miss_resrv_wsel_st0,
output wire[`WORD_WIDTH-1:0] miss_resrv_data_st0,
output wire[`REQS_BITS-1:0] miss_resrv_tid_st0,
output wire[`REQ_TAG_WIDTH-1:0] miss_resrv_tag_st0,
output wire miss_resrv_rw_st0,
output wire[WORD_SIZE-1:0] miss_resrv_byteen_st0,
output wire miss_resrv_is_snp_st0,
output wire miss_resrv_snp_invalidate_st0,
input wire miss_resrv_pop_st2
input wire schedule_st0,
output wire dequeue_valid_st0,
output wire[`LINE_ADDR_WIDTH-1:0] dequeue_addr_st0,
output wire[`UP(`WORD_SELECT_WIDTH)-1:0] dequeue_wsel_st0,
output wire[`WORD_WIDTH-1:0] dequeue_data_st0,
output wire[`REQS_BITS-1:0] dequeue_tid_st0,
output wire[`REQ_TAG_WIDTH-1:0] dequeue_tag_st0,
output wire dequeue_rw_st0,
output wire[WORD_SIZE-1:0] dequeue_byteen_st0,
output wire dequeue_is_snp_st0,
output wire dequeue_snp_inv_st0,
input wire dequeue_st3
);
localparam FULL_DISTANCE = 2; // need 2 cycles window to prevent pipeline lock
localparam FULL_DISTANCE = 3; // need 3 cycles window to prevent pipeline lock
wire [`MRVQ_METADATA_WIDTH-1:0] metadata_table;
`NO_RW_RAM_CHECK reg [`LINE_ADDR_WIDTH-1:0] addr_table [MRVQ_SIZE-1:0];
@@ -88,8 +87,8 @@ module VX_cache_miss_resrv #(
`STATIC_ASSERT(MRVQ_SIZE > FULL_DISTANCE, ("invalid size"))
assign miss_resrv_full = (size == $bits(size)'(MRVQ_SIZE));
assign miss_resrv_almfull = (size >= $bits(size)'(MRVQ_SIZE-FULL_DISTANCE));
assign enqueue_full = (size == $bits(size)'(MRVQ_SIZE));
assign enqueue_almfull = (size >= $bits(size)'(MRVQ_SIZE-FULL_DISTANCE));
wire [MRVQ_SIZE-1:0] valid_address_match;
for (genvar i = 0; i < MRVQ_SIZE; i++) begin
@@ -100,18 +99,18 @@ module VX_cache_miss_resrv #(
wire dequeue_ready = valid_table[schedule_ptr] && ready_table[schedule_ptr];
assign miss_resrv_valid_st0 = dequeue_ready;
assign miss_resrv_addr_st0 = addr_table[schedule_ptr];
assign {miss_resrv_data_st0,
miss_resrv_tid_st0,
miss_resrv_tag_st0,
miss_resrv_rw_st0,
miss_resrv_byteen_st0,
miss_resrv_wsel_st0,
miss_resrv_is_snp_st0,
miss_resrv_snp_invalidate_st0} = metadata_table;
assign dequeue_valid_st0 = dequeue_ready;
assign dequeue_addr_st0 = addr_table[schedule_ptr];
assign {dequeue_data_st0,
dequeue_tid_st0,
dequeue_tag_st0,
dequeue_rw_st0,
dequeue_byteen_st0,
dequeue_wsel_st0,
dequeue_is_snp_st0,
dequeue_snp_inv_st0} = metadata_table;
wire msrq_push = miss_add && !is_msrq_st2;
wire msrq_push = enqueue_st3 && !enqueue_msrq_st3;
wire [`LOG2UP(MRVQ_SIZE)-1:0] head_ptr_n = head_ptr + $bits(head_ptr)'(1);
@@ -130,30 +129,30 @@ module VX_cache_miss_resrv #(
ready_table <= ready_table | valid_address_match;
end
if (miss_add) begin
assert(!miss_resrv_full);
if (is_msrq_st2) begin
if (enqueue_st3) begin
assert(!enqueue_full);
if (enqueue_msrq_st3) begin
// returning missed msrq entry, restore schedule
valid_table[restore_ptr] <= 1;
ready_table[restore_ptr] <= init_ready_state_st2;
ready_table[restore_ptr] <= enqueue_ready_st3;
restore_ptr <= restore_ptr + $bits(restore_ptr)'(1);
schedule_ptr <= head_ptr;
end else begin
valid_table[tail_ptr] <= 1;
ready_table[tail_ptr] <= init_ready_state_st2;
addr_table[tail_ptr] <= miss_add_addr;
ready_table[tail_ptr] <= enqueue_ready_st3;
addr_table[tail_ptr] <= enqueue_addr_st3;
tail_ptr <= tail_ptr + $bits(tail_ptr)'(1);
size <= size + $bits(size)'(1);
end
end else if (miss_resrv_pop_st2) begin
end else if (dequeue_st3) begin
head_ptr <= head_ptr_n;
restore_ptr <= head_ptr_n;
valid_table[head_ptr] <= 0;
size <= size - $bits(size)'(1);
end
if (miss_resrv_schedule_st0) begin
assert(miss_resrv_valid_st0);
if (schedule_st0) begin
assert(dequeue_valid_st0);
valid_table[schedule_ptr] <= 0;
schedule_ptr <= schedule_ptr + $bits(schedule_ptr)'(1);
end
@@ -171,24 +170,25 @@ module VX_cache_miss_resrv #(
.waddr(tail_ptr),
.raddr(schedule_ptr),
.wren(msrq_push),
.byteen(1'b1),
.rden(1'b1),
.din({miss_add_data, miss_add_tid, miss_add_tag, miss_add_rw, miss_add_byteen, miss_add_wsel, miss_add_is_snp, miss_add_snp_invalidate}),
.din({enqueue_data_st3, enqueue_tid_st3, enqueue_tag_st3, enqueue_rw_st3, enqueue_byteen_st3, enqueue_wsel_st3, enqueue_is_snp_st3, enqueue_snp_inv_st3}),
.dout(metadata_table)
);
`ifdef DBG_PRINT_CACHE_MSRQ
always @(posedge clk) begin
if (miss_add || miss_resrv_schedule_st0 || miss_resrv_pop_st2) begin
if (miss_add) begin
if (is_msrq_st2)
$display("%t: cache%0d:%0d msrq-restore addr%0d=%0h ready=%b", $time, CACHE_ID, BANK_ID, restore_ptr, `LINE_TO_BYTE_ADDR(miss_add_addr, BANK_ID), init_ready_state_st2);
if (enqueue_st3 || schedule_st0 || dequeue_st3) begin
if (enqueue_st3) begin
if (enqueue_msrq_st3)
$display("%t: cache%0d:%0d msrq-restore addr%0d=%0h ready=%b", $time, CACHE_ID, BANK_ID, restore_ptr, `LINE_TO_BYTE_ADDR(enqueue_addr_st3, BANK_ID), enqueue_ready_st3);
else
$display("%t: cache%0d:%0d msrq-enq addr%0d=%0h ready=%b wid=%0d PC=%0h", $time, CACHE_ID, BANK_ID, tail_ptr, `LINE_TO_BYTE_ADDR(miss_add_addr, BANK_ID), init_ready_state_st2, debug_wid_st2, debug_pc_st2);
$display("%t: cache%0d:%0d msrq-enq addr%0d=%0h ready=%b wid=%0d PC=%0h", $time, CACHE_ID, BANK_ID, tail_ptr, `LINE_TO_BYTE_ADDR(enqueue_addr_st3, BANK_ID), enqueue_ready_st3, debug_wid_st3, debug_pc_st3);
end
if (miss_resrv_schedule_st0)
$display("%t: cache%0d:%0d msrq-schedule addr%0d=%0h wid=%0d PC=%0h", $time, CACHE_ID, BANK_ID, schedule_ptr, `LINE_TO_BYTE_ADDR(miss_resrv_addr_st0, BANK_ID), debug_wid_st0, debug_pc_st0);
if (miss_resrv_pop_st2)
$display("%t: cache%0d:%0d msrq-deq addr%0d wid=%0d PC=%0h", $time, CACHE_ID, BANK_ID, head_ptr, debug_wid_st2, debug_pc_st2);
if (schedule_st0)
$display("%t: cache%0d:%0d msrq-schedule addr%0d=%0h wid=%0d PC=%0h", $time, CACHE_ID, BANK_ID, schedule_ptr, `LINE_TO_BYTE_ADDR(dequeue_addr_st0, BANK_ID), debug_wid_st0, debug_pc_st0);
if (dequeue_st3)
$display("%t: cache%0d:%0d msrq-deq addr%0d wid=%0d PC=%0h", $time, CACHE_ID, BANK_ID, head_ptr, debug_wid_st3, debug_pc_st3);
$write("%t: cache%0d:%0d msrq-table", $time, CACHE_ID, BANK_ID);
for (integer j = 0; j < MRVQ_SIZE; j++) begin
if (valid_table[j]) begin

138
hw/rtl/cache/VX_data_access.v vendored Normal file
View File

@@ -0,0 +1,138 @@
`include "VX_cache_config.vh"
module VX_data_access #(
parameter CACHE_ID = 0,
parameter BANK_ID = 0,
// Size of cache in bytes
parameter CACHE_SIZE = 1,
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE = 1,
// Number of banks
parameter NUM_BANKS = 1,
// Size of a word in bytes
parameter WORD_SIZE = 1,
// Enable cache writeable
parameter WRITE_ENABLE = 0,
// Enable dram update
parameter DRAM_ENABLE = 0,
// size of tag id in core request tag
parameter CORE_TAG_ID_BITS = 0
) (
input wire clk,
input wire reset,
`ifdef DBG_CORE_REQ_INFO
`IGNORE_WARNINGS_BEGIN
input wire[31:0] debug_pc_st2,
input wire[`NR_BITS-1:0] debug_rd_st2,
input wire[`NW_BITS-1:0] debug_wid_st2,
input wire[`UP(CORE_TAG_ID_BITS)-1:0] debug_tagid_st2,
`IGNORE_WARNINGS_END
`endif
input wire stall,
input wire valid_req_st2,
input wire writeen_st2,
`IGNORE_WARNINGS_BEGIN
input wire[`LINE_ADDR_WIDTH-1:0] addr_st2,
`IGNORE_WARNINGS_END
input wire writefill_st2,
input wire[`WORD_WIDTH-1:0] writeword_st2,
input wire[`BANK_LINE_WIDTH-1:0] writedata_st2,
input wire[WORD_SIZE-1:0] mem_byteen_st2,
input wire[`UP(`WORD_SELECT_WIDTH)-1:0] wordsel_st2,
output wire[`WORD_WIDTH-1:0] readword_st2,
output wire[`BANK_LINE_WIDTH-1:0] readdata_st2,
output wire[BANK_LINE_SIZE-1:0] dirtyb_st2
);
wire[BANK_LINE_SIZE-1:0] qual_read_dirtyb_st2;
wire[`BANK_LINE_WIDTH-1:0] qual_read_data_st2;
wire[BANK_LINE_SIZE-1:0] use_read_dirtyb_st2;
wire[`BANK_LINE_WIDTH-1:0] use_read_data_st2;
wire[`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] use_byte_enable;
wire[`BANK_LINE_WIDTH-1:0] use_write_data;
wire use_write_enable;
wire[`LINE_SELECT_BITS-1:0] addrline_st2 = addr_st2[`LINE_SELECT_BITS-1:0];
VX_data_store #(
.CACHE_SIZE (CACHE_SIZE),
.BANK_LINE_SIZE (BANK_LINE_SIZE),
.NUM_BANKS (NUM_BANKS),
.WORD_SIZE (WORD_SIZE)
) data_store (
.clk (clk),
.reset (reset),
.read_addr (addrline_st2),
.read_dirtyb (qual_read_dirtyb_st2),
.read_data (qual_read_data_st2),
.write_enable(use_write_enable),
.write_fill (writefill_st2),
.byte_enable (use_byte_enable),
.write_addr (addrline_st2),
.write_data (use_write_data)
);
assign use_read_dirtyb_st2= qual_read_dirtyb_st2;
assign use_read_data_st2 = qual_read_data_st2;
if (`WORD_SELECT_WIDTH != 0) begin
wire [`WORD_WIDTH-1:0] readword = use_read_data_st2[wordsel_st2 * `WORD_WIDTH +: `WORD_WIDTH];
for (genvar i = 0; i < WORD_SIZE; i++) begin
assign readword_st2[i * 8 +: 8] = readword[i * 8 +: 8] & {8{mem_byteen_st2[i]}};
end
end else begin
for (genvar i = 0; i < WORD_SIZE; i++) begin
assign readword_st2[i * 8 +: 8] = use_read_data_st2[i * 8 +: 8] & {8{mem_byteen_st2[i]}};
end
end
wire [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] byte_enable;
wire [`BANK_LINE_WIDTH-1:0] data_write;
for (genvar i = 0; i < `BANK_LINE_WORDS; i++) begin
wire word_sel = ((`WORD_SELECT_WIDTH == 0) || (wordsel_st2 == `UP(`WORD_SELECT_WIDTH)'(i)));
assign byte_enable[i] = writefill_st2 ? {WORD_SIZE{1'b1}} :
word_sel ? mem_byteen_st2 :
{WORD_SIZE{1'b0}};
assign data_write[i * `WORD_WIDTH +: `WORD_WIDTH] = writefill_st2 ? writedata_st2[i * `WORD_WIDTH +: `WORD_WIDTH] : writeword_st2;
end
assign use_write_enable = valid_req_st2 && writeen_st2 && !stall;
assign use_byte_enable = byte_enable;
assign use_write_data = data_write;
assign dirtyb_st2 = use_read_dirtyb_st2;
assign readdata_st2 = use_read_data_st2;
`ifdef DBG_PRINT_CACHE_DATA
always @(posedge clk) begin
if (valid_req_st2 && !stall) begin
if (use_write_enable) begin
if (writefill_st2) begin
$display("%t: cache%0d:%0d data-fill: addr=%0h, dirty=%b, blk_addr=%0d, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st2, BANK_ID), dirtyb_st2, addrline_st2, use_write_data);
end else begin
$display("%t: cache%0d:%0d data-write: addr=%0h, wid=%0d, PC=%0h, dirty=%b, blk_addr=%0d, wsel=%0d, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st2, BANK_ID), debug_wid_st2, debug_pc_st2, dirtyb_st2, addrline_st2, wordsel_st2, writeword_st2);
end
end else begin
$display("%t: cache%0d:%0d data-read: addr=%0h, wid=%0d, PC=%0h, dirty=%b, blk_addr=%0d, wsel=%0d, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st2, BANK_ID), debug_wid_st2, debug_pc_st2, dirtyb_st2, addrline_st2, wordsel_st2, qual_read_data_st2);
end
end
end
`endif
endmodule

53
hw/rtl/cache/VX_data_store.v vendored Normal file
View File

@@ -0,0 +1,53 @@
`include "VX_cache_config.vh"
module VX_data_store #(
// Size of cache in bytes
parameter CACHE_SIZE = 1,
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE = 1,
// Number of banks
parameter NUM_BANKS = 1,
// Size of a word in bytes
parameter WORD_SIZE = 1
) (
input wire clk,
input wire reset,
input wire write_enable,
input wire write_fill,
input wire[`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] byte_enable,
input wire[`LINE_SELECT_BITS-1:0] write_addr,
input wire[`BANK_LINE_WIDTH-1:0] write_data,
input wire[`LINE_SELECT_BITS-1:0] read_addr,
output wire[`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] read_dirtyb,
output wire[`BANK_LINE_WIDTH-1:0] read_data
);
`UNUSED_VAR (reset)
reg [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] dirtyb[`BANK_LINE_COUNT-1:0];
always @(posedge clk) begin
if (write_enable) begin
dirtyb[write_addr] <= write_fill ? 0 : (dirtyb[write_addr] | byte_enable);
end
end
assign read_dirtyb = dirtyb [read_addr];
VX_dp_ram #(
.DATAW(`BANK_LINE_WORDS * WORD_SIZE * 8),
.SIZE(`BANK_LINE_COUNT),
.BYTEENW(`BANK_LINE_WORDS * WORD_SIZE),
.BUFFERED(0),
.RWCHECK(1)
) data (
.clk(clk),
.waddr(write_addr),
.raddr(read_addr),
.wren(write_enable),
.byteen(byte_enable),
.rden(1'b1),
.din(write_data),
.dout(read_data)
);
endmodule

101
hw/rtl/cache/VX_tag_data_access.v → hw/rtl/cache/VX_tag_access.v vendored
View File

@@ -1,6 +1,6 @@
`include "VX_cache_config.vh"
module VX_tag_data_access #(
module VX_tag_access #(
parameter CACHE_ID = 0,
parameter BANK_ID = 0,
@@ -25,8 +25,6 @@ module VX_tag_data_access #(
input wire clk,
input wire reset,
input wire stall,
`ifdef DBG_CORE_REQ_INFO
`IGNORE_WARNINGS_BEGIN
input wire[31:0] debug_pc_st1,
@@ -36,6 +34,8 @@ module VX_tag_data_access #(
`IGNORE_WARNINGS_END
`endif
input wire stall,
input wire is_snp_st1,
input wire snp_invalidate_st1,
@@ -43,132 +43,89 @@ module VX_tag_data_access #(
input wire valid_req_st1,
input wire writefill_st1,
input wire[`WORD_WIDTH-1:0] writeword_st1,
input wire[`BANK_LINE_WIDTH-1:0] writedata_st1,
`IGNORE_WARNINGS_BEGIN
input wire mem_rw_st1,
input wire[WORD_SIZE-1:0] mem_byteen_st1,
input wire[`UP(`WORD_SELECT_WIDTH)-1:0] wordsel_st1,
`IGNORE_WARNINGS_END
input wire force_miss_st1,
output wire[`WORD_WIDTH-1:0] readword_st1,
output wire[`BANK_LINE_WIDTH-1:0] readdata_st1,
output wire[`TAG_SELECT_BITS-1:0] readtag_st1,
output wire miss_st1,
output wire dirty_st1,
output wire[BANK_LINE_SIZE-1:0] dirtyb_st1
output wire writeen_st1
);
wire qual_read_valid_st1;
wire qual_read_dirty_st1;
wire[BANK_LINE_SIZE-1:0] qual_read_dirtyb_st1;
wire[`TAG_SELECT_BITS-1:0] qual_read_tag_st1;
wire[`BANK_LINE_WIDTH-1:0] qual_read_data_st1;
wire use_read_valid_st1;
wire use_read_dirty_st1;
wire[BANK_LINE_SIZE-1:0] use_read_dirtyb_st1;
wire[`TAG_SELECT_BITS-1:0] use_read_tag_st1;
wire[`BANK_LINE_WIDTH-1:0] use_read_data_st1;
wire[`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] use_write_enable;
wire[`BANK_LINE_WIDTH-1:0] use_write_data;
wire use_invalidate;
wire use_write_enable;
wire use_invalidate;
wire[`TAG_SELECT_BITS-1:0] addrtag_st1 = addr_st1[`TAG_LINE_ADDR_RNG];
wire[`LINE_SELECT_BITS-1:0] addrline_st1 = addr_st1[`LINE_SELECT_BITS-1:0];
VX_tag_data_store #(
.CACHE_SIZE (CACHE_SIZE),
VX_tag_store #(
.CACHE_SIZE (CACHE_SIZE),
.BANK_LINE_SIZE (BANK_LINE_SIZE),
.NUM_BANKS (NUM_BANKS),
.WORD_SIZE (WORD_SIZE)
) tag_data_store (
.NUM_BANKS (NUM_BANKS),
.WORD_SIZE (WORD_SIZE)
) tag_store (
.clk (clk),
.reset (reset),
.stall (stall),
.read_addr (addrline_st1),
.read_valid (qual_read_valid_st1),
.read_dirty (qual_read_dirty_st1),
.read_dirtyb (qual_read_dirtyb_st1),
.read_tag (qual_read_tag_st1),
.read_data (qual_read_data_st1),
.invalidate (use_invalidate),
.write_enable(use_write_enable),
.write_fill (writefill_st1),
.write_addr (addrline_st1),
.tag_index (addrtag_st1),
.write_data (use_write_data)
.write_tag (addrtag_st1)
);
assign use_read_valid_st1 = qual_read_valid_st1 || !DRAM_ENABLE; // If shared memory, always valid
assign use_read_dirty_st1 = qual_read_dirty_st1 && DRAM_ENABLE && WRITE_ENABLE; // Dirty only applies in Dcache
assign use_read_tag_st1 = DRAM_ENABLE ? qual_read_tag_st1 : addrtag_st1; // Tag is always the same in SM
assign use_read_dirtyb_st1= qual_read_dirtyb_st1;
assign use_read_data_st1 = qual_read_data_st1;
if (`WORD_SELECT_WIDTH != 0) begin
wire [`WORD_WIDTH-1:0] readword = use_read_data_st1[wordsel_st1 * `WORD_WIDTH +: `WORD_WIDTH];
for (genvar i = 0; i < WORD_SIZE; i++) begin
assign readword_st1[i * 8 +: 8] = readword[i * 8 +: 8] & {8{mem_byteen_st1[i]}};
end
end else begin
for (genvar i = 0; i < WORD_SIZE; i++) begin
assign readword_st1[i * 8 +: 8] = use_read_data_st1[i * 8 +: 8] & {8{mem_byteen_st1[i]}};
end
end
// use "case equality" to handle uninitialized tag when block entry is not valid
wire tags_match = use_read_valid_st1 && (addrtag_st1 === use_read_tag_st1);
wire [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] write_enable;
wire [`BANK_LINE_WIDTH-1:0] data_write;
wire normal_write = valid_req_st1
&& mem_rw_st1
&& use_read_valid_st1
&& !writefill_st1
&& !is_snp_st1
&& !miss_st1
&& !force_miss_st1
&& mem_rw_st1
&& use_read_valid_st1;
&& !force_miss_st1;
wire fill_write = valid_req_st1 && writefill_st1
&& !tags_match // disable redundant fills because the block could be dirty
&& !stall; // do not fill the cache on stalls to preserve writeback
&& !tags_match; // discard redundant fills because the block could be dirty
for (genvar i = 0; i < `BANK_LINE_WORDS; i++) begin
wire normal_write_w = ((`WORD_SELECT_WIDTH == 0) || (wordsel_st1 == `UP(`WORD_SELECT_WIDTH)'(i)))
&& normal_write;
assign use_write_enable = normal_write || fill_write;
assign write_enable[i] = fill_write ? {WORD_SIZE{1'b1}} :
normal_write_w ? mem_byteen_st1 :
{WORD_SIZE{1'b0}};
assign data_write[i * `WORD_WIDTH +: `WORD_WIDTH] = writefill_st1 ? writedata_st1[i * `WORD_WIDTH +: `WORD_WIDTH] : writeword_st1;
end
assign use_write_enable = write_enable;
assign use_write_data = data_write;
assign use_invalidate = valid_req_st1 && is_snp_st1 && tags_match
&& (use_read_dirty_st1 || snp_invalidate_st1) // block is dirty or need to force invalidation
&& !force_miss_st1
&& !stall; // do not invalidate the cache on stalls to preserve writeback
&& !force_miss_st1;
wire core_req_miss = valid_req_st1 && !is_snp_st1 && !writefill_st1 // is core request
&& (!use_read_valid_st1 || !tags_match); // block missing or has wrong tag
assign miss_st1 = core_req_miss;
assign dirty_st1 = valid_req_st1 && use_read_valid_st1 && use_read_dirty_st1;
assign dirtyb_st1 = use_read_dirtyb_st1;
assign readdata_st1 = use_read_data_st1;
assign readtag_st1 = use_read_tag_st1;
assign miss_st1 = core_req_miss;
assign dirty_st1 = valid_req_st1 && use_read_valid_st1 && use_read_dirty_st1;
assign readtag_st1 = use_read_tag_st1;
assign writeen_st1 = use_write_enable;
`ifdef DBG_PRINT_CACHE_DATA
always @(posedge clk) begin
if (valid_req_st1) begin
if (valid_req_st1 && !stall) begin
if (writefill_st1 && use_read_valid_st1 && tags_match) begin
$display("%t: warning: redundant fill - addr=%0h", $time, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID));
end
@@ -176,12 +133,12 @@ module VX_tag_data_access #(
$display("%t: cache%0d:%0d data-miss: addr=%0h, wid=%0d, PC=%0h, valid=%b, tagmatch=%b, blk_addr=%0d, tag_id=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID), debug_wid_st1, debug_pc_st1, use_read_dirty_st1, tags_match, addrline_st1, addrtag_st1);
end else if ((| use_write_enable)) begin
if (writefill_st1) begin
$display("%t: cache%0d:%0d data-fill: addr=%0h, dirty=%b, blk_addr=%0d, tag_id=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID), dirtyb_st1, addrline_st1, addrtag_st1, use_write_data);
$display("%t: cache%0d:%0d data-fill: addr=%0h, blk_addr=%0d, tag_id=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID), addrline_st1, addrtag_st1);
end else begin
$display("%t: cache%0d:%0d data-write: addr=%0h, wid=%0d, PC=%0h, dirty=%b, blk_addr=%0d, tag_id=%0h, wsel=%0d, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID), debug_wid_st1, debug_pc_st1, dirtyb_st1, addrline_st1, addrtag_st1, wordsel_st1, writeword_st1);
$display("%t: cache%0d:%0d data-write: addr=%0h, wid=%0d, PC=%0h, blk_addr=%0d, tag_id=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID), debug_wid_st1, debug_pc_st1, addrline_st1, addrtag_st1);
end
end else begin
$display("%t: cache%0d:%0d data-read: addr=%0h, wid=%0d, PC=%0h, dirty=%b, blk_addr=%0d, tag_id=%0h, wsel=%0d, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID), debug_wid_st1, debug_pc_st1, dirtyb_st1, addrline_st1, qual_read_tag_st1, wordsel_st1, qual_read_data_st1);
$display("%t: cache%0d:%0d data-read: addr=%0h, wid=%0d, PC=%0h, blk_addr=%0d, tag_id=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID), debug_wid_st1, debug_pc_st1, addrline_st1, qual_read_tag_st1);
end
end
end

68
hw/rtl/cache/VX_tag_data_store.v → hw/rtl/cache/VX_tag_store.v vendored
View File

@@ -1,6 +1,6 @@
`include "VX_cache_config.vh"
module VX_tag_data_store #(
module VX_tag_store #(
// Size of cache in bytes
parameter CACHE_SIZE = 1,
// Size of line inside a bank in bytes
@@ -11,29 +11,23 @@ module VX_tag_data_store #(
parameter WORD_SIZE = 1
) (
input wire clk,
input wire reset,
input wire reset,
input wire[`LINE_SELECT_BITS-1:0] read_addr,
output wire read_valid,
output wire read_dirty,
output wire[`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] read_dirtyb,
output wire[`TAG_SELECT_BITS-1:0] read_tag,
output wire[`BANK_LINE_WIDTH-1:0] read_data,
input wire stall,
input wire invalidate,
input wire[`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] write_enable,
input wire write_enable,
input wire write_fill,
input wire[`LINE_SELECT_BITS-1:0] write_addr,
input wire[`TAG_SELECT_BITS-1:0] tag_index,
input wire[`BANK_LINE_WIDTH-1:0] write_data
input wire[`TAG_SELECT_BITS-1:0] write_tag,
input wire invalidate,
input wire[`LINE_SELECT_BITS-1:0] read_addr,
output wire[`TAG_SELECT_BITS-1:0] read_tag,
output wire read_valid,
output wire read_dirty
);
reg [`BANK_LINE_COUNT-1:0] dirty;
reg [`BANK_LINE_COUNT-1:0] valid;
assign read_valid = valid[read_addr];
assign read_dirty = dirty[read_addr];
wire do_write = (| write_enable);
reg [`BANK_LINE_COUNT-1:0] valid;
always @(posedge clk) begin
if (reset) begin
@@ -41,8 +35,8 @@ module VX_tag_data_store #(
valid[i] <= 0;
dirty[i] <= 0;
end
end else begin
if (do_write) begin
end else if(!stall) begin
if (write_enable) begin
assert(!invalidate);
dirty[write_addr] <= !write_fill;
valid[write_addr] <= 1;
@@ -52,14 +46,6 @@ module VX_tag_data_store #(
end
end
reg [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] dirtyb[`BANK_LINE_COUNT-1:0];
always @(posedge clk) begin
if (do_write) begin
dirtyb[write_addr] <= write_fill ? 0 : (dirtyb[write_addr] | write_enable);
end
end
assign read_dirtyb = dirtyb [read_addr];
VX_dp_ram #(
.DATAW(`TAG_SELECT_BITS),
.SIZE(`BANK_LINE_COUNT),
@@ -67,29 +53,17 @@ module VX_tag_data_store #(
.BUFFERED(0),
.RWCHECK(1)
) tags (
.clk(clk),
.waddr(write_addr),
.raddr(read_addr),
.wren(do_write),
.rden(1'b1),
.din(tag_index),
.dout(read_tag)
);
VX_dp_ram #(
.DATAW(`BANK_LINE_WORDS * WORD_SIZE * 8),
.SIZE(`BANK_LINE_COUNT),
.BYTEENW(`BANK_LINE_WORDS * WORD_SIZE),
.BUFFERED(0),
.RWCHECK(1)
) data (
.clk(clk),
.waddr(write_addr),
.raddr(read_addr),
.wren(write_enable),
.byteen(1'b1),
.rden(1'b1),
.din(write_data),
.dout(read_data)
);
.din(write_tag),
.dout(read_tag)
);
assign read_valid = valid[read_addr];
assign read_dirty = dirty[read_addr];
endmodule

51
hw/rtl/libs/VX_dp_ram.v
View File

@@ -13,7 +13,8 @@ module VX_dp_ram #(
input wire clk,
input wire [ADDRW-1:0] waddr,
input wire [ADDRW-1:0] raddr,
input wire [BYTEENW-1:0] wren,
input wire wren,
input wire [BYTEENW-1:0] byteen,
input wire rden,
input wire [DATAW-1:0] din,
output wire [DATAW-1:0] dout
@@ -26,14 +27,16 @@ module VX_dp_ram #(
if (BYTEENW > 1) begin
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[waddr][i * 8 +: 8] <= din[i * 8 +: 8];
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i * 8 +: 8] <= din[i * 8 +: 8];
end
end
end
end else begin
always @(posedge clk) begin
if (wren)
if (wren && byteen)
mem[waddr] <= din;
end
end
@@ -48,14 +51,14 @@ module VX_dp_ram #(
wire writing;
if (BYTEENW > 1) begin
assign writing = (| wren);
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
din_r[i * 8 +: 8] <= wren[i] ? din[i * 8 +: 8] : mem[waddr][i * 8 +: 8];
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
din_r[i * 8 +: 8] <= byteen[i] ? din[i * 8 +: 8] : mem[waddr][i * 8 +: 8];
end
end
end
end else begin
assign writing = wren;
always @(posedge clk) begin
din_r <= din;
end
@@ -63,7 +66,7 @@ module VX_dp_ram #(
reg bypass_r;
always @(posedge clk) begin
bypass_r <= writing && (raddr == waddr);
bypass_r <= wren && (raddr == waddr);
end
assign dout = bypass_r ? din_r : dout_r;
@@ -81,14 +84,16 @@ module VX_dp_ram #(
if (BYTEENW > 1) begin
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[waddr][i * 8 +: 8] <= din[i * 8 +: 8];
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i * 8 +: 8] <= din[i * 8 +: 8];
end
end
end
end else begin
always @(posedge clk) begin
if (wren)
if (wren && byteen)
mem[waddr] <= din;
end
end
@@ -98,14 +103,14 @@ module VX_dp_ram #(
wire writing;
if (BYTEENW > 1) begin
assign writing = (| wren);
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
din_r[i * 8 +: 8] <= wren[i] ? din[i * 8 +: 8] : mem[waddr][i * 8 +: 8];
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
din_r[i * 8 +: 8] <= byteen[i] ? din[i * 8 +: 8] : mem[waddr][i * 8 +: 8];
end
end
end
end else begin
assign writing = wren;
always @(posedge clk) begin
din_r <= din;
end
@@ -127,14 +132,16 @@ module VX_dp_ram #(
if (BYTEENW > 1) begin
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[waddr][i * 8 +: 8] <= din[i * 8 +: 8];
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i * 8 +: 8] <= din[i * 8 +: 8];
end
end
end
end else begin
always @(posedge clk) begin
if (wren)
if (wren && byteen)
mem[waddr] <= din;
end
end

2
hw/rtl/libs/VX_generic_queue.v
View File

@@ -114,6 +114,7 @@ module VX_generic_queue #(
.waddr(wr_ptr_a),
.raddr(rd_ptr_a),
.wren(push),
.byteen(1'b1),
.rden(pop),
.din(data_in),
.dout(data_out)
@@ -166,6 +167,7 @@ module VX_generic_queue #(
.waddr(wr_ptr_r),
.raddr(rd_ptr_n_r),
.wren(push),
.byteen(1'b1),
.rden(pop),
.din(data_in),
.dout(dout)

2
hw/scripts/scope.json
View File

@@ -203,9 +203,11 @@
"?valid_st0": 1,
"?valid_st1": 1,
"?valid_st2": 1,
"?valid_st3": 1,
"addr_st0": 32,
"addr_st1": 32,
"addr_st2": 32,
"addr_st3": 32,
"is_mrvq_st1": 1,
"miss_st1": 1,
"dirty_st1": 1,