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scope refactoring

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This commit is contained in:
Blaise Tine
2020-10-03 18:53:21 -04:00
parent 878c89861b
commit 4e1007e5b2
28 changed files with 1014 additions and 693 deletions
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11
driver/opae/Makefile
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@@ -1,11 +1,14 @@
OPAE_HOME ?= /tools/opae/1.4.0
#CXXFLAGS += -std=c++11 -O2 -DNDEBUG -Wall -Wextra -pedantic -Wfatal-errors
CXXFLAGS += -std=c++11 -O0 -g -Wall -Wextra -pedantic -Wfatal-errors
CXXFLAGS += -I../include -I$(OPAE_HOME)/include -I../../hw
LDFLAGS += -L$(OPAE_HOME)/lib
SCOPE=1
# stack execution protection
LDFLAGS +=-z noexecstack
@@ -22,7 +25,11 @@ CXXFLAGS += -fPIC
CXXFLAGS += -DDUMP_PERF_STATS
# Enable scope analyzer
#CXXFLAGS += -DSCOPE
# Enable scope analyzer
ifdef SCOPE
CXXFLAGS += -DSCOPE
SET_SCOPE = SCOPE=1
endif
LDFLAGS += -shared
@@ -64,7 +71,7 @@ vlsim: $(SRCS) opae-vlsim
$(CXX) $(CXXFLAGS) -L./vlsim -DUSE_VLSIM $(SRCS) $(LDFLAGS) $(VLSIM_LIBS) -o $(PROJECT_VLSIM)
opae-vlsim:
$(MAKE) -C vlsim
$(SET_SCOPE) $(MAKE) -C vlsim
vortex.o: vortex.cpp
$(CXX) $(CXXFLAGS) -c vortex.cpp -o $@

24
driver/opae/vlsim/Makefile
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@@ -12,6 +12,8 @@ DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_MSRQ
DBG_PRINT_FLAGS += -DDBG_PRINT_DRAM
DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE
DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE
DBG_PRINT_FLAGS += -DDBG_CORE_REQ_INFO
DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE
DBG_FLAGS += $(DBG_PRINT_FLAGS)
DBG_FLAGS += -DDBG_CORE_REQ_INFO
@@ -21,7 +23,8 @@ DBG_FLAGS += -DDBG_CORE_REQ_INFO
CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0
#CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=1
#DEBUG=1
DEBUG=1
#SCOPE=1
CFLAGS += -fPIC
@@ -34,7 +37,7 @@ LDFLAGS += -shared -pthread
TOP = vortex_afu_shim
RTL_DIR = ../../../hw/rtl
RTL_DIR=../../../hw/rtl
SRCS = fpga.cpp opae_sim.cpp
SRCS += $(RTL_DIR)/fp_cores/svdpi/float_dpi.cpp
@@ -60,20 +63,27 @@ else
CFLAGS += -DNDEBUG
endif
# Enable scope analyzer
ifdef SCOPE
VL_FLAGS += -DSCOPE
CFLAGS += -DSCOPE
SCOPE_CFG = scope
endif
VL_FLAGS += -DNOPAE
CFLAGS += -DNOPAE
# Enable scope analyzer
#VL_FLAGS += -DSCOPE
#CFLAGS += -DSCOPE
RTL_INCLUDE += -I../../../hw/opae -I../../../hw/opae/ccip
PROJECT = libopae-c-vlsim.so
all: $(PROJECT)
# generate scope data
scope: ../../../hw/scripts/scope.json
../../../hw/scripts/scope.py $(RTL_INCLUDE) $(CONFIGS) -cc ../scope-defs.h -vl ../../../hw/rtl/scope-defs.vh ../../../hw/scripts/scope.json
$(PROJECT): $(SRCS)
$(PROJECT): $(SRCS) $(SCOPE_CFG)
verilator --exe --cc $(TOP) --top-module $(TOP) $(RTL_INCLUDE) $(VL_FLAGS) $(SRCS) -CFLAGS '$(CFLAGS)' -LDFLAGS '$(LDFLAGS)' -o ../$(PROJECT)
OPT_FAST="-O0 -g" make -j -C obj_dir -f V$(TOP).mk

4
driver/opae/vlsim/opae_sim.cpp
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@@ -135,6 +135,10 @@ void opae_sim::step() {
this->sRxPort_bus();
this->sTxPort_bus();
this->avs_bus();
#ifndef NDEBUG
fflush(stdout);
#endif
}
void opae_sim::eval() {

4
driver/opae/vortex.cpp
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@@ -509,11 +509,11 @@ extern int vx_start(vx_device_h hdevice) {
// start execution
CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CMD_TYPE, CMD_RUN));
#ifdef SCOPE
/*#ifdef SCOPE
sleep(15);
vx_scope_stop(device->fpga, 0);
exit(0);
#endif
#endif*/
return 0;
}

137
driver/opae/vx_scope.cpp
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@@ -14,6 +14,9 @@
#include <VX_config.h>
#include "vx_scope.h"
#include "vortex_afu.h"
#include "scope-defs.h"
#define SCOPE_FRAME_WIDTH 1768
#define CHECK_RES(_expr) \
do { \
@@ -28,132 +31,6 @@
#define MMIO_SCOPE_READ (AFU_IMAGE_MMIO_SCOPE_READ * 4)
#define MMIO_SCOPE_WRITE (AFU_IMAGE_MMIO_SCOPE_WRITE * 4)
struct scope_signal_t {
int width;
const char* name;
};
constexpr int ilog2(int n) {
return (n > 1) ? 1 + ilog2(n >> 1) : 0;
}
static constexpr int NW_BITS = ilog2(NUM_WARPS);
#ifdef EXT_F_ENABLE
static constexpr int NR_BITS = ilog2(64);
#else
static constexpr int NR_BITS = ilog2(32);
#endif
static constexpr int EX_BITS = 3;
static constexpr int OP_BITS = 4;
static constexpr int MOD_BITS = 3;
static constexpr int ICORE_TAG_WIDTH = NW_BITS;
static constexpr int DCORE_TAG_WIDTH = ilog2(LSUQ_SIZE);
static constexpr scope_signal_t scope_signals[] = {
{ 32, "dram_req_addr" },
{ 1, "dram_req_rw" },
{ 16, "dram_req_byteen" },
{ 128, "dram_req_data" },
{ 29, "dram_req_tag" },
{ 128, "dram_rsp_data" },
{ 29, "dram_rsp_tag" },
{ 32, "snp_req_addr" },
{ 1, "snp_req_invalidate" },
{ 16, "snp_req_tag" },
{ 16, "snp_rsp_tag" },
{ NW_BITS, "icache_req_wid" },
{ 32, "icache_req_addr" },
{ ICORE_TAG_WIDTH, "icache_req_tag" },
{ 32, "icache_rsp_data" },
{ ICORE_TAG_WIDTH, "icache_rsp_tag" },
{ NW_BITS, "dcache_req_wid" },
{ 32, "dcache_req_pc" },
{ NUM_THREADS * 32, "dcache_req_addr" },
{ 1, "dcache_req_rw" },
{ NUM_THREADS * 4, "dcache_req_byteen" },
{ NUM_THREADS * 32, "dcache_req_data" },
{ DCORE_TAG_WIDTH, "dcache_req_tag" },
{ NUM_THREADS * 32, "dcache_rsp_data" },
{ DCORE_TAG_WIDTH, "dcache_rsp_tag" },
{ NW_BITS, "issue_wid" },
{ NUM_THREADS, "issue_tmask" },
{ 32, "issue_pc" },
{ EX_BITS, "issue_ex_type" },
{ OP_BITS, "issue_op_type" },
{ MOD_BITS, "issue_op_mod" },
{ 1, "issue_wb" },
{ NR_BITS, "issue_rd" },
{ NR_BITS, "issue_rs1" },
{ NR_BITS, "issue_rs2" },
{ NR_BITS, "issue_rs3" },
{ 32, "issue_imm" },
{ 1, "issue_rs1_is_pc" },
{ 1, "issue_rs2_is_imm" },
{ NW_BITS, "gpr_rsp_wid" },
{ 32, "gpr_rsp_pc" },
{ NUM_THREADS * 32, "gpr_rsp_a" },
{ NUM_THREADS * 32, "gpr_rsp_b" },
{ NUM_THREADS * 32, "gpr_rsp_c" },
{ NW_BITS, "writeback_wid" },
{ 32, "writeback_pc" },
{ NR_BITS, "writeback_rd" },
{ NUM_THREADS * 32, "writeback_data" },
{ 32, "bank_addr_st0" },
{ 32, "bank_addr_st1" },
{ 32, "bank_addr_st2" },
{ 1, "scope_bank_is_mrvq_st1" },
{ 1, "scope_bank_miss_st1" },
{ 1, "scope_bank_dirty_st1" },
{ 1, "scope_bank_force_miss_st1" },
///////////////////////////////////////////////////////////////////////////
{ 1, "dram_req_valid" },
{ 1, "dram_req_ready" },
{ 1, "dram_rsp_valid" },
{ 1, "dram_rsp_ready" },
{ 1, "snp_req_valid" },
{ 1, "snp_req_ready" },
{ 1, "snp_rsp_valid" },
{ 1, "snp_rsp_ready" },
{ 1, "icache_req_valid" },
{ 1, "icache_req_ready" },
{ 1, "icache_rsp_valid" },
{ 1, "icache_rsp_ready" },
{ NUM_THREADS, "dcache_req_valid" },
{ 1, "dcache_req_ready" },
{ NUM_THREADS, "dcache_rsp_valid" },
{ 1, "dcache_rsp_ready" },
{ 1, "bank_valid_st0" },
{ 1, "bank_valid_st1" },
{ 1, "bank_valid_st2" },
{ 1, "bank_stall_pipe" },
{ 1, "issue_valid" },
{ 1, "issue_ready" },
{ 1, "gpr_rsp_valid" },
{ 1, "writeback_valid" },
{ 1, "scoreboard_delay" },
{ 1, "gpr_delay" },
{ 1, "execute_delay" },
{ 1, "busy" },
};
static constexpr int num_signals = sizeof(scope_signals) / sizeof(scope_signal_t);
constexpr int calcFrameWidth(int index = 0) {
@@ -161,7 +38,6 @@ constexpr int calcFrameWidth(int index = 0) {
}
static constexpr int fwidth = calcFrameWidth();
static_assert(fwidth == 1766, "invalid size");
int vx_scope_start(fpga_handle hfpga, uint64_t delay) {
if (nullptr == hfpga)
@@ -190,9 +66,14 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) {
std::ofstream ofs("vx_scope.vcd");
ofs << "$version Generated by Vortex Scope $end" << std::endl;
ofs << "$timescale 1 ns $end" << std::endl;
ofs << "$var reg 1 0 clk $end" << std::endl;
for (int i = 0; i < num_signals; ++i) {
ofs << "$var reg " << scope_signals[i].width << " " << (i+1) << " " << scope_signals[i].name << " $end" << std::endl;
}
ofs << "enddefinitions $end" << std::endl;
uint64_t frame_width, max_frames, data_valid;
@@ -237,7 +118,7 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) {
ofs << "b1 0" << std::endl;
uint64_t delta;
fpga_result res = fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &delta);
auto res = fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &delta);
assert(res == FPGA_OK);
while (delta != 0) {

2
driver/rtlsim/Makefile
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@@ -12,6 +12,8 @@ DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_MSRQ
DBG_PRINT_FLAGS += -DDBG_PRINT_DRAM
DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE
DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE
DBG_PRINT_FLAGS += -DDBG_CORE_REQ_INFO
DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE
DBG_FLAGS += $(DBG_PRINT_FLAGS)
DBG_FLAGS += -DDBG_CORE_REQ_INFO

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driver/tests/basic/kernel.bin
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11
driver/tests/basic/kernel.dump
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@@ -74,7 +74,7 @@ Disassembly of section .text:
800000e0: 0005006b 0x5006b
800000e4: 00002197 auipc gp,0x2
800000e8: c8418193 addi gp,gp,-892 # 80001d68 <__global_pointer$>
800000ec: f14025f3 csrr a1,mhartid
800000ec: 022025f3 csrr a1,0x22
800000f0: 00a59593 slli a1,a1,0xa
800000f4: 02002673 csrr a2,0x20
800000f8: 00261613 slli a2,a2,0x2
@@ -122,7 +122,7 @@ Disassembly of section .text:
80000158: 00008067 ret
8000015c <vx_thread_gid>:
8000015c: f1402573 csrr a0,mhartid
8000015c: 02202573 csrr a0,0x22
80000160: 00008067 ret
80000164 <vx_core_id>:
@@ -458,13 +458,12 @@ Disassembly of section .comment:
Disassembly of section .riscv.attributes:
00000000 <.riscv.attributes>:
0: 2041 jal 80 <_start-0x7fffff80>
0: 2541 jal 680 <_start-0x7ffff980>
2: 0000 unimp
4: 7200 flw fs0,32(a2)
6: 7369 lui t1,0xffffa
8: 01007663 bgeu zero,a6,14 <_start-0x7fffffec>
c: 0016 c.slli zero,0x5
e: 0000 unimp
c: 0000001b 0x1b
10: 1004 addi s1,sp,32
12: 7205 lui tp,0xfffe1
14: 3376 fld ft6,376(sp)
@@ -473,4 +472,4 @@ Disassembly of section .riscv.attributes:
1a: 5f30 lw a2,120(a4)
1c: 326d jal fffff9c6 <__global_pointer$+0x7fffdc5e>
1e: 3070 fld fa2,224(s0)
...
20: 665f 7032 0030 0x307032665f

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driver/tests/basic/kernel.elf
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