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core_wrapper: Use finished and !reset to determine termination

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Hansung Kim
2024-06-11 16:27:23 -07:00
parent de10d5a957
commit 5218292b6f
1 changed files with 27 additions and 21 deletions
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48
hw/rtl/VX_core_wrapper.sv
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@@ -495,28 +495,34 @@ module Vortex import VX_gpu_pkg::*; #(
// .busy(busy)
// );
always @(*) begin
if (busy === 1'b0) begin
$display("---------------- no more active warps ----------------");
`ifdef SIMULATION
if ($time >= 60000) begin
$display("simulation has probably ended. exiting");
@(posedge clock) $finish();
always @(posedge clock) begin
if (!reset) begin
if (finished) begin
`ifdef SIMULATION
$display("---------------- core%2d has no more active warps ----------------", CORE_ID);
$display("simulation has ended. exiting");
$finish();
`endif
// `ifdef SIMULATION
// if ($time >= 60000) begin
// $display("simulation has probably ended. exiting");
// @(posedge clock) $finish();
// end
// `endif
// TODO: lane assumed to be 4
// `ifndef SYNTHESIS
// for (integer j = 0; j < `NUM_WARPS; j++) begin
// $display("warp %2d", j);
// for (integer k = 0; k < `NUM_REGS; k += 1)
// $display("x%2d: %08x %08x %08x %08x", k,
// pipeline.issue.gpr_stage.iports[/*thread*/0].dp_ram1.not_out_reg.reg_dump.ram[j * `NUM_REGS + k],
// pipeline.issue.gpr_stage.iports[/*thread*/1].dp_ram1.not_out_reg.reg_dump.ram[j * `NUM_REGS + k],
// pipeline.issue.gpr_stage.iports[/*thread*/2].dp_ram1.not_out_reg.reg_dump.ram[j * `NUM_REGS + k],
// pipeline.issue.gpr_stage.iports[/*thread*/3].dp_ram1.not_out_reg.reg_dump.ram[j * `NUM_REGS + k]);
// end
// `endif
// @(posedge clock) $finish();
end
`endif
// TODO: lane assumed to be 4
// `ifndef SYNTHESIS
// for (integer j = 0; j < `NUM_WARPS; j++) begin
// $display("warp %2d", j);
// for (integer k = 0; k < `NUM_REGS; k += 1)
// $display("x%2d: %08x %08x %08x %08x", k,
// pipeline.issue.gpr_stage.iports[/*thread*/0].dp_ram1.not_out_reg.reg_dump.ram[j * `NUM_REGS + k],
// pipeline.issue.gpr_stage.iports[/*thread*/1].dp_ram1.not_out_reg.reg_dump.ram[j * `NUM_REGS + k],
// pipeline.issue.gpr_stage.iports[/*thread*/2].dp_ram1.not_out_reg.reg_dump.ram[j * `NUM_REGS + k],
// pipeline.issue.gpr_stage.iports[/*thread*/3].dp_ram1.not_out_reg.reg_dump.ram[j * `NUM_REGS + k]);
// end
// `endif
// @(posedge clock) $finish();
end
end