registering execute units inputs
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@@ -38,7 +38,8 @@ module VX_instr_demux (
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wire alu_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_ALU);
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VX_skid_buffer #(
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.DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `ALU_BITS + `MOD_BITS + 32 + 1 + 1 + `NR_BITS + 1 + `NT_BITS + (2 * `NUM_THREADS * 32))
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.DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `ALU_BITS + `MOD_BITS + 32 + 1 + 1 + `NR_BITS + 1 + `NT_BITS + (2 * `NUM_THREADS * 32)),
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.OUTPUT_REG (1)
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) alu_buffer (
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.clk (clk),
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.reset (reset),
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@@ -56,7 +57,8 @@ module VX_instr_demux (
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wire lsu_is_fence = `LSU_IS_FENCE(ibuffer_if.op_mod);
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VX_skid_buffer #(
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.DATAW (`NW_BITS + `NUM_THREADS + 32 + `LSU_BITS + 1 + 32 + `NR_BITS + 1 + (2 * `NUM_THREADS * 32))
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.DATAW (`NW_BITS + `NUM_THREADS + 32 + `LSU_BITS + 1 + 32 + `NR_BITS + 1 + (2 * `NUM_THREADS * 32)),
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.OUTPUT_REG (1)
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) lsu_buffer (
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.clk (clk),
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.reset (reset),
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@@ -73,7 +75,8 @@ module VX_instr_demux (
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wire csr_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_CSR);
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VX_skid_buffer #(
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.DATAW (`NW_BITS + `NUM_THREADS + 32 + `CSR_BITS + `CSR_ADDR_BITS + `NR_BITS + 1 + 1 + `NR_BITS + 32)
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.DATAW (`NW_BITS + `NUM_THREADS + 32 + `CSR_BITS + `CSR_ADDR_BITS + `NR_BITS + 1 + 1 + `NR_BITS + 32),
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.OUTPUT_REG (1)
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) csr_buffer (
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.clk (clk),
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.reset (reset),
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@@ -91,7 +94,8 @@ module VX_instr_demux (
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wire fpu_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_FPU);
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VX_skid_buffer #(
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.DATAW (`NW_BITS + `NUM_THREADS + 32 + `FPU_BITS + `MOD_BITS + `NR_BITS + 1 + (3 * `NUM_THREADS * 32))
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.DATAW (`NW_BITS + `NUM_THREADS + 32 + `FPU_BITS + `MOD_BITS + `NR_BITS + 1 + (3 * `NUM_THREADS * 32)),
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.OUTPUT_REG (1)
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) fpu_buffer (
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.clk (clk),
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.reset (reset),
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@@ -112,7 +116,8 @@ module VX_instr_demux (
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wire gpu_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_GPU);
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VX_skid_buffer #(
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.DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `GPU_BITS + `NR_BITS + 1 + (`NUM_THREADS * 32 + 32))
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.DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `GPU_BITS + `NR_BITS + 1 + (`NUM_THREADS * 32 + 32)),
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.OUTPUT_REG (1)
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) gpu_buffer (
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.clk (clk),
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.reset (reset),
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