wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

pipeline refactoring - fmax >= 222 mhz

Browse Source
This commit is contained in:
Blaise Tine
2020-08-14 21:50:14 -07:00
parent 71a46d04b9
commit 6c12391338
107 changed files with 1392 additions and 1239 deletions
Download Patch File Download Diff File Expand all files Collapse all files

60
hw/rtl/VX_fpu_unit.v
View File

@@ -14,9 +14,27 @@ module VX_fpu_unit #(
// outputs
VX_fpu_to_cmt_if fpu_commit_if
);
assign csr_to_fpu_if.warp_num = fpu_req_if.warp_num;
wire [`FRM_BITS-1:0] frm = (fpu_req_if.frm == `FRM_DYN) ? csr_to_fpu_if.frm : fpu_req_if.frm;
VX_fpu_req_if fpu_req_tmp_if();
// resolve dynamic FRM
wire [`FRM_BITS-1:0] frm, frm_tmp;
assign csr_to_fpu_if.wid = fpu_req_if.wid;
assign frm = (fpu_req_if.frm == `FRM_DYN) ? csr_to_fpu_if.frm : fpu_req_if.frm;
// use a skid buffer since fpcore has realtime backpressure
VX_elastic_buffer #(
.DATAW (`ISTAG_BITS + `NW_BITS + 32 + `FPU_BITS + `FRM_BITS + (3 * `NUM_THREADS * 32)),
.SIZE (0)
) input_buffer (
.clk (clk),
.reset (reset),
.valid_in (fpu_req_if.valid),
.ready_in (fpu_req_if.ready),
.data_in ({fpu_req_if.issue_tag, fpu_req_if.wid, fpu_req_if.curr_PC, fpu_req_if.op, frm, fpu_req_if.rs1_data, fpu_req_if.rs2_data, fpu_req_if.rs3_data}),
.data_out ({fpu_req_tmp_if.issue_tag, fpu_req_tmp_if.wid, fpu_req_tmp_if.curr_PC, fpu_req_tmp_if.op, frm_tmp, fpu_req_tmp_if.rs1_data, fpu_req_tmp_if.rs2_data, fpu_req_tmp_if.rs3_data}),
.ready_out (fpu_req_tmp_if.ready),
.valid_out (fpu_req_tmp_if.valid)
);
`ifdef SYNTHESIS
@@ -24,17 +42,17 @@ module VX_fpu_unit #(
.clk (clk),
.reset (reset),
.valid_in (fpu_req_if.valid),
.ready_in (fpu_req_if.ready),
.valid_in (fpu_req_tmp_if.valid),
.ready_in (fpu_req_tmp_if.ready),
.tag_in (fpu_req_if.issue_tag),
.tag_in (fpu_req_tmp_if.issue_tag),
.op (fpu_req_if.fpu_op),
.frm (frm),
.op (fpu_req_tmp_if.op),
.frm (frm_tmp),
.dataa (fpu_req_if.rs1_data),
.datab (fpu_req_if.rs2_data),
.datac (fpu_req_if.rs3_data),
.dataa (fpu_req_tmp_if.rs1_data),
.datab (fpu_req_tmp_if.rs2_data),
.datac (fpu_req_tmp_if.rs3_data),
.result (fpu_commit_if.data),
.has_fflags (fpu_commit_if.has_fflags),
@@ -42,7 +60,7 @@ module VX_fpu_unit #(
.tag_out (fpu_commit_if.issue_tag),
.ready_out (fpu_commit_if.ready),
.ready_out (1'b1),
.valid_out (fpu_commit_if.valid)
);
@@ -57,17 +75,17 @@ module VX_fpu_unit #(
.clk (clk),
.reset (reset),
.valid_in (fpu_req_if.valid),
.ready_in (fpu_req_if.ready),
.valid_in (fpu_req_tmp_if.valid),
.ready_in (fpu_req_tmp_if.ready),
.tag_in (fpu_req_if.issue_tag),
.tag_in (fpu_req_tmp_if.issue_tag),
.op (fpu_req_if.fpu_op),
.frm (frm),
.op (fpu_req_tmp_if.op),
.frm (frm_tmp),
.dataa (fpu_req_if.rs1_data),
.datab (fpu_req_if.rs2_data),
.datac (fpu_req_if.rs3_data),
.dataa (fpu_req_tmp_if.rs1_data),
.datab (fpu_req_tmp_if.rs2_data),
.datac (fpu_req_tmp_if.rs3_data),
.result (fpu_commit_if.data),
.has_fflags (fpu_commit_if.has_fflags),
@@ -75,7 +93,7 @@ module VX_fpu_unit #(
.tag_out (fpu_commit_if.issue_tag),
.ready_out (fpu_commit_if.ready),
.ready_out (1'b1),
.valid_out (fpu_commit_if.valid)
);