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[debug] Print warp id for memtraces

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This commit is contained in:
Hansung Kim
2023-09-26 13:36:22 -07:00
parent d34177ea9c
commit 719b8048ab
1 changed files with 4 additions and 0 deletions
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4
sim/simx/execute.cpp
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@@ -693,6 +693,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
trace->mem_addrs.at(t).push_back({mem_addr, mem_bytes}); trace->mem_addrs.at(t).push_back({mem_addr, mem_bytes});
DP(2, "LOAD MEM: CYCLE=" << std::dec << SimPlatform::instance().cycles() DP(2, "LOAD MEM: CYCLE=" << std::dec << SimPlatform::instance().cycles()
<< ", CORE=" << core_->id() << ", CORE=" << core_->id()
<< ", WARP=" << id_
<< ", THREAD=" << t << ", THREAD=" << t
<< ", ADDRESS=0x" << std::hex << mem_addr << ", ADDRESS=0x" << std::hex << mem_addr
<< ", DATA=0x" << mem_data << std::dec << ", DATA=0x" << mem_data << std::dec
@@ -738,6 +739,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
*result_ptr = mem_data; *result_ptr = mem_data;
DP(2, "LOAD MEM: CYCLE=" << std::dec << SimPlatform::instance().cycles() DP(2, "LOAD MEM: CYCLE=" << std::dec << SimPlatform::instance().cycles()
<< ", CORE=" << core_->id() << ", CORE=" << core_->id()
<< ", WARP=" << id_
<< ", VLEN=" << vl_ << ", VLEN=" << vl_
<< ", VID=" << i << ", VID=" << i
<< ", ADDRESS=0x" << std::hex << mem_addr << ", ADDRESS=0x" << std::hex << mem_addr
@@ -775,6 +777,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
trace->mem_addrs.at(t).push_back({mem_addr, mem_bytes}); trace->mem_addrs.at(t).push_back({mem_addr, mem_bytes});
DP(2, "STORE MEM: CYCLE=" << std::dec << SimPlatform::instance().cycles() DP(2, "STORE MEM: CYCLE=" << std::dec << SimPlatform::instance().cycles()
<< ", CORE=" << core_->id() << ", CORE=" << core_->id()
<< ", WARP=" << id_
<< ", THREAD=" << t << ", THREAD=" << t
<< ", ADDRESS=0x" << std::hex << mem_addr << ", ADDRESS=0x" << std::hex << mem_addr
<< ", DATA=0x" << mem_data << std::dec << ", DATA=0x" << mem_data << std::dec
@@ -800,6 +803,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
core_->dcache_write(&mem_data, mem_addr, 4); core_->dcache_write(&mem_data, mem_addr, 4);
DP(2, "STORE MEM: CYCLE=" << std::dec << SimPlatform::instance().cycles() DP(2, "STORE MEM: CYCLE=" << std::dec << SimPlatform::instance().cycles()
<< ", CORE=" << core_->id() << ", CORE=" << core_->id()
<< ", WARP=" << id_
<< ", VLEN=" << vl_ << ", VLEN=" << vl_
<< ", VID=" << i << ", VID=" << i
<< ", ADDRESS=0x" << std::hex << mem_addr << ", ADDRESS=0x" << std::hex << mem_addr