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added generic_queue_ll

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This commit is contained in:
Blaise Tine
2020-03-05 10:43:15 -05:00
parent 721d22ae86
commit 730c36ef18
4 changed files with 112 additions and 6 deletions
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8
rtl/VX_cache/VX_bank.v
View File

@@ -62,7 +62,7 @@ module VX_bank (
reg snrq_hazard_st0;
assign snrq_valid_st0 = !snrq_empty;
VX_generic_queue #(.DATAW(32), .SIZE(`SNRQ_SIZE)) snr_queue(
VX_generic_queue_ll #(.DATAW(32), .SIZE(`SNRQ_SIZE)) snr_queue(
.clk (clk),
.reset (reset),
.push (snp_req),
@@ -82,7 +82,7 @@ module VX_bank (
assign dram_fill_accept = !dfpq_full;
VX_generic_queue #(.DATAW(32+(`BANK_LINE_SIZE_WORDS*32)), .SIZE(`DFPQ_SIZE)) dfp_queue(
VX_generic_queue_ll #(.DATAW(32+(`BANK_LINE_SIZE_WORDS*32)), .SIZE(`DFPQ_SIZE)) dfp_queue(
.clk (clk),
.reset (reset),
.push (dram_fill_rsp),
@@ -385,7 +385,7 @@ module VX_bank (
wire cwbq_full;
wire cwbq_empty;
assign bank_wb_valid = !cwbq_empty;
VX_generic_queue #(.DATAW( `vx_clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1+1) + 32), .SIZE(`CWBQ_SIZE)) cwb_queue(
VX_generic_queue_ll #(.DATAW( `vx_clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1+1) + 32), .SIZE(`CWBQ_SIZE)) cwb_queue(
.clk (clk),
.reset (reset),
@@ -425,7 +425,7 @@ module VX_bank (
assign dram_fill_req_addr = addr_st2;
assign dram_wb_req = !dwbq_empty;
VX_generic_queue #(.DATAW( 1 + 32 + (`BANK_LINE_SIZE_WORDS * 32) + 1 + 1), .SIZE(`DWBQ_SIZE)) dwb_queue(
VX_generic_queue_ll #(.DATAW( 1 + 32 + (`BANK_LINE_SIZE_WORDS * 32) + 1 + 1), .SIZE(`DWBQ_SIZE)) dwb_queue(
.clk (clk),
.reset (reset),

2
rtl/VX_cache/VX_cache_dfq_queue.v
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@@ -33,7 +33,7 @@ module VX_cache_dfq_queue
wire push_qual = dfqq_push && !dfqq_full;
wire pop_qual = dfqq_pop && use_empty && !out_empty && !dfqq_empty;
VX_generic_queue #(.DATAW(`NUMBER_BANKS * (1+32)), .SIZE(`DFQQ_SIZE)) dfqq_queue(
VX_generic_queue_ll #(.DATAW(`NUMBER_BANKS * (1+32)), .SIZE(`DFQQ_SIZE)) dfqq_queue(
.clk (clk),
.reset (reset),
.push (push_qual),

2
rtl/VX_cache/VX_cache_req_queue.v
View File

@@ -69,7 +69,7 @@ module VX_cache_req_queue (
wire push_qual = reqq_push && !reqq_full;
wire pop_qual = reqq_pop && use_empty && !out_empty && !reqq_empty;
VX_generic_queue #(.DATAW( (`NUMBER_REQUESTS * (1+32+32)) + 5 + 2 + (`NW_M1+1) + 3 + 3 ), .SIZE(`REQQ_SIZE)) reqq_queue(
VX_generic_queue_ll #(.DATAW( (`NUMBER_REQUESTS * (1+32+32)) + 5 + 2 + (`NW_M1+1) + 3 + 3 ), .SIZE(`REQQ_SIZE)) reqq_queue(
.clk (clk),
.reset (reset),
.push (push_qual),

106
rtl/VX_generic_queue_ll.v Normal file
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@@ -0,0 +1,106 @@
module VX_generic_queue_ll
#(
parameter DATAW = 4,
parameter SIZE = 277
)
(
input wire clk,
input wire reset,
input wire push,
input wire[DATAW-1:0] in_data,
input wire pop,
output wire[DATAW-1:0] out_data,
output wire empty,
output wire full
);
reg[DATAW-1:0] data[SIZE-1:0], curr_r, head_r;
reg[$clog2(SIZE+1)-1:0] size_r;
reg[$clog2(SIZE)-1:0] wr_ctr_r;
reg[$clog2(SIZE)-1:0] rd_ptr_r, rd_next_ptr_r;
reg empty_r, full_r, bypass_r;
wire reading, writing;
assign reading = pop && !empty;
assign writing = push && !full;
if (SIZE == 1) begin
always @(posedge clk) begin
if (reset) begin
size_r <= 0;
end else begin
if (writing && !reading) begin
size_r <= 1;
end else if (reading && !writing) begin
size_r <= 0;
end
if (writing) begin
head_r <= in_data;
end
end
end
assign out_data = head_r;
assign empty = (size_r == 0);
assign full = (size_r != 0) && !pop;
end else begin
always @(posedge clk) begin
if (reset) begin
wr_ctr_r <= 0;
end else begin
if (writing)
wr_ctr_r <= wr_ctr_r + 1;
end
end
always @(posedge clk) begin
if (reset) begin
size_r <= 0;
empty_r <= 1;
full_r <= 0;
end else begin
if (writing && !reading) begin
size_r <= size_r + 1;
empty_r <= 0;
if (size_r == SIZE-1)
full_r <= 1;
end else if (reading && !writing) begin
size_r <= size_r - 1;
if (size_r == 1)
empty_r <= 1;
full_r <= 0;
end
end
end
always @(posedge clk) begin
if (reset) begin
rd_ptr_r <= 0;
rd_next_ptr_r <= 1;
bypass_r <= 0;
end else begin
if (reading) begin
if (SIZE == 2) begin
rd_ptr_r <= rd_next_ptr_r;
rd_next_ptr_r <= ~rd_next_ptr_r;
end else if (SIZE > 2) begin
rd_ptr_r <= rd_next_ptr_r;
rd_next_ptr_r <= rd_ptr_r + 2;
end
end
bypass_r <= writing && (empty_r || (1 == size_r && reading));
curr_r <= in_data;
head_r <= data[reading ? rd_next_ptr_r : rd_ptr_r];
end
end
assign out_data = bypass_r ? curr_r : head_r;
assign empty = empty_r;
assign full = full_r;
end
endmodule