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Finished cache, dram imp + interfaces left

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This commit is contained in:
felsabbagh3
2020-03-03 19:42:33 -08:00
parent e2e053ff7b
commit 733d00aba9
4 changed files with 329 additions and 38 deletions
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140
rtl/VX_cache/VX_bank.v
View File

@@ -119,6 +119,16 @@ module VX_bank (
wire [2:0] mrvq_mem_read_st0;
wire [2:0] mrvq_mem_write_st0;
wire miss_add;
wire[31:0] miss_add_addr;
wire[31:0] miss_add_data;
wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] miss_add_tid;
wire[4:0] miss_add_rd;
wire[1:0] miss_add_wb;
wire[`NW_M1:0] miss_add_warp_num;
wire[2:0] miss_add_mem_read;
wire[2:0] miss_add_mem_write;
VX_cache_miss_resrv mrvq_queue(
.clk (clk),
.reset (reset),
@@ -151,16 +161,12 @@ module VX_bank (
.miss_resrv_mem_write_st0(mrvq_mem_write_st0)
);
wire stall_st0;
wire stall_st1;
wire stall_st2;
wire stall_bank_pipe;
assign stall_st1 = stall_st2;
assign stall_st0 = stall_st1;
assign dfpq_pop = !dfpq_empty && !stall_st0;
assign mrvq_pop = !dfpq_pop && mrvq_valid_st0 && !stall_st0;
assign reqq_pop = !mrvq_pop && reqq_req_st0 && !stall_st0;
assign dfpq_pop = !dfpq_empty && !stall_bank_pipe;
assign mrvq_pop = !dfpq_pop && mrvq_valid_st0 && !stall_bank_pipe;
assign reqq_pop = !mrvq_pop && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0];
wire qual_is_fill_st0;
@@ -191,14 +197,14 @@ module VX_bank (
assign qual_writedata_st0 = dfpq_pop ? dfpq_filldata_st0 : 0;
assign qual_inst_meta_st0 = mrvq_pop ? {mrvq_rd_st0, mrvq_wb_st0, mrvq_warp_num_st0, mrvq_mem_read_st0, mrvq_mem_write_st0, mrvq_tid_st0} :
reqq_pop ? {reqq_rd_st0, reqq_wb_st0, reqq_warp_num_st0, reqq_mem_read_st0, reqq_mem_write_st0, reqq_tid_st0} :
assign qual_inst_meta_st0 = mrvq_pop ? {mrvq_rd_st0 , mrvq_wb_st0 , mrvq_warp_num_st0 , mrvq_mem_read_st0 , mrvq_mem_write_st0 , mrvq_tid_st0 } :
reqq_pop ? {reqq_req_rd_st0, reqq_req_wb_st0, reqq_req_warp_num_st0, reqq_req_mem_read_st0, reqq_req_mem_write_st0, reqq_req_tid_st0} :
0;
VX_generic_register #(.N( 1 + 32 + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_RNG*32) + 1)) s0_1_c0 (
.clk (clk),
.reset(reset),
.stall(stall_st1),
.stall(stall_bank_pipe),
.flush(0),
.in ({qual_valid_st0, qual_addr_st0, qual_writeword_st0, qual_inst_meta_st0, qual_is_fill_st0, qual_writedata_st0}),
.out ({valid_st1[0] , addr_st1[0] , writeword_st1[0] , inst_meta_st1[0] , is_fill_st1[0] , writedata_st1[0]})
@@ -210,8 +216,8 @@ module VX_bank (
VX_generic_register #(.N( 1 + 32 + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_RNG*32) + 1)) s0_1_cc (
.clk (clk),
.reset(reset),
.stall(stall_st1),
.flush(is_fill_st1),
.stall(stall_bank_pipe),
.flush(0),
.in ({valid_st1[curr_stage-1], addr_st1[curr_stage-1], writeword_st1[curr_stage-1], inst_meta_st1[curr_stage-1], is_fill_st1[curr_stage-1] , writedata_st1[curr_stage-1]}),
.out ({valid_st1[curr_stage] , addr_st1[curr_stage] , writeword_st1[curr_stage] , inst_meta_st1[curr_stage] , is_fill_st1[curr_stage] , writedata_st1[curr_stage] })
);
@@ -221,34 +227,122 @@ module VX_bank (
wire[31:0] readword_st1e;
wire[`BANK_LINE_SIZE_RNG][31:0] readdata_st1e;
wire[`TAG_SELECT_SIZE_RNG] readtag_st1e;
wire miss_st1e;
wire dirty_st1e;
wire [4:0] rd_st1e;
wire [1:0] wb_st1e;
wire [`NW_M1:0] warp_num_st1e;
wire [2:0] mem_read_st1e;
wire [2:0] mem_write_st1e;
wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] tid_st1e;
assign {rd_st1e, wb_st1e, warp_num_st1e, mem_read_st1e, mem_write_st1e, tid_st1e} = inst_meta_st1[`STAGE_1_CYCLES-1];
VX_tag_data_access VX_tag_data_access(
.clk (clk),
.reset (reset),
.valid_st10 (valid_st10),
.stall (stall),
// Read start
// Initial Read
.readaddr_st10 (addr_st1[0]),
// Write stuff
// Actual Read/Write
.valid_req_st1e(valid_st1[`STAGE_1_CYCLES-1]),
.writefill_st1e(is_fill_st1[`STAGE_1_CYCLES-1]),
.writeaddr_st1e(addr_st1[`STAGE_1_CYCLES-1]),
.writeword_st1e(writeword_st1[`STAGE_1_CYCLES-1]),
.mem_write_st1e(mem_write_st1e), // TODO
.writedata_st1e(writedata_st1[`STAGE_1_CYCLES-1]),
.mem_write_st1e(mem_write_st1e),
.mem_read_st1e (mem_read_st1e),
// Fill info
.is_fill_st1e (is_fill_st1[`STAGE_1_CYCLES-1]),
.filldata_st1e (writedata_st1[`STAGE_1_CYCLES-1]),
// Read stuff + result
.mem_read_st1e (mem_read_st1e), // TODO
// Read Data
.readword_st1e (readword_st1e),
.readdata_st1e (readdata_st1e),
.readtag_st1e (readtag_st1e),
.miss_st1e (miss_st1e),
.dirty_st1e (dirty_st1e)
);
wire qual_valid_st1e_2 = valid_st1[`STAGE_1_CYCLES-1] && !is_fill_st1[`STAGE_1_CYCLES-1];
wire valid_st2;
wire[31:0] addr_st2;
wire[31:0] writeword_st2;
wire[31:0] readword_st2;
wire[`BANK_LINE_SIZE_RNG][31:0] readdata_st2;
wire miss_st2;
wire dirty_st2;
wire[`REQ_INST_META_SIZE-1:0] inst_meta_st2;
wire[`TAG_SELECT_SIZE_RNG] readtag_st2;
VX_generic_register #(.N( 1 + 32 + 32 + 32 + (`BANK_LINE_SIZE_RNG * 32) + 1 + 1 + `REQ_INST_META_SIZE + `TAG_SELECT_NUM_BITS)) st_1e_2 (
.clk (clk),
.reset(reset),
.stall(stall_bank_pipe),
.flush(0),
.in ({qual_valid_st1e_2, addr_st1[`STAGE_1_CYCLES-1], writeword_st1[`STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, inst_meta_st1[`STAGE_1_CYCLES-1]}),
.out ({valid_st2 , addr_st2 , writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , inst_meta_st2 })
);
// Enqueue to miss reserv if it's a valid miss
assign miss_add = valid_st2 && miss_st2;
assign miss_add_addr = addr_st2;
assign miss_add_data = writeword_st2;
assign {miss_add_rd, miss_add_wb, miss_add_warp_num, miss_add_mem_read, miss_add_mem_write, miss_add_tid} = inst_meta_st2;
// Enqueue to CWB Queue
wire cwbq_push = valid_st2 && !miss_st2;
wire [31:0] cwbq_data = readword_st2;
wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] cwbq_tid = miss_add_tid;
wire [4:0] cwbq_rd = miss_add_rd;
wire [1:0] cwbq_wb = miss_add_wb;
wire [`NW_M1:0] cwbq_warp_num = miss_add_warp_num;
wire cwbq_full;
wire cwbq_empty;
VX_generic_queue #(.DATAW( `vx_clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1+1) + 32), .SIZE(`CWBQ_SIZE)) cwb_queue(
.clk (clk),
.reset (reset),
.push (cwbq_push),
.in_data ({cwbq_tid, cwbq_rd, cwbq_wb, cwbq_warp_num, cwbq_data}),
.pop (bank_wb_pop),
.out_data({bank_wb_tid, bank_wb_rd, bank_wb_wb, bank_wb_warp_num, bank_wb_data}),
.empty (cwbq_empty),
.full (cwbq_full)
);
// Enqueue to DWB Queue
wire dwbq_push = valid_st2 && miss_st2 && dirty_st2;
wire[31:0] dwbq_req_addr = {readtag_st2, addr_st2[`LINE_SELECT_ADDR_END:0]}
wire[`BANK_LINE_SIZE_RNG][31:0] dwbq_req_data = readdata_st2;
wire dwbq_empty;
wire dwbq_full;
assign dram_wb_req = !dwbq_empty;
VX_generic_queue #(.DATAW( 1 + 32 + (`BANK_LINE_SIZE_RNG * 32) + 1 + 1), .SIZE(`DWBQ_SIZE)) dwb_queue(
.clk (clk),
.reset (reset),
.push (dwbq_push),
.in_data ({dwbq_req_addr, dwbq_req_data}),
.pop (dram_wb_queue_pop),
.out_data({dram_wb_req_addr, dram_wb_req_data}),
.empty (dwbq_empty),
.full (dwbq_full)
);
assign stall_bank_pipe = (cwbq_push && cwbq_full) || (dwbq_push && dwbq_full) || (miss_add && mrvq_full);
endmodule

2
rtl/VX_cache/VX_cache.v
View File

@@ -1,7 +1,5 @@
`include "VX_cache_config.v"
`include "VX_cache_config.v"
module VX_cache (
input wire clk,

173
rtl/VX_cache/VX_tag_data_access.v
View File

@@ -3,24 +3,187 @@
module VX_tag_data_access (
input wire clk,
input wire reset,
input wire stall,
input wire valid_st10,
input wire is_fill_st10,
// Initial Reading
input wire[31:0] readaddr_st10,
input wire[`BANK_LINE_SIZE_RNG][31:0] filldata_st10,
// Write/Read Logic
input wire valid_req_st1e,
input wire writefill_st1e,
input wire[31:0] writeaddr_st1e,
input wire[31:0] writeword_st1e,
input wire[`BANK_LINE_SIZE_RNG][31:0] writedata_st1e,
input wire[2:0] mem_write_st1e,
input wire[2:0] mem_read_st1e,
output wire[31:0] readword_st1e,
output wire[`BANK_LINE_SIZE_RNG][31:0] readdata_st1e,
output wire miss_st1e
output wire[`TAG_SELECT_SIZE_RNG] readtag_st1e,
output wire miss_st1e,
output wire dirty_st1e
);
reg[`BANK_LINE_SIZE_RNG][31:0] readdata_st[`STAGE_1_CYCLES-1:0];
endmodule
reg read_valid_st1c[`STAGE_1_CYCLES-1:0];
reg read_dirty_st1c[`STAGE_1_CYCLES-1:0];
reg[`TAG_SELECT_SIZE_RNG] read_tag_st1c [`STAGE_1_CYCLES-1:0];
reg[`BANK_LINE_SIZE_RNG][31:0] read_data_st1c [`STAGE_1_CYCLES-1:0];
wire qual_read_valid_st1;
wire qual_read_dirty_st1;
wire[`TAG_SELECT_SIZE_RNG] qual_read_tag_st1;
wire[`BANK_LINE_SIZE_RNG][31:0] qual_read_data_st1;
wire use_read_valid_st1e;
wire use_read_dirty_st1e;
wire[`TAG_SELECT_SIZE_RNG] use_read_tag_st1e;
wire[`BANK_LINE_SIZE_RNG][31:0] use_read_data_st1e;
wire[`BANK_LINE_SIZE_RNG][3:0] use_write_enable;
wire[`BANK_LINE_SIZE_RNG][31:0] use_write_data;
VX_tag_data_structure VX_tag_data_structure(
.clk (clk),
.reset (reset),
.read_addr (readaddr_st10),
.read_valid (qual_read_valid_st1),
.read_dirty (qual_read_dirty_st1),
.read_tag (qual_read_tag_st1),
.read_data (qual_read_data_st1)
.write_enable(use_write_enable),
.write_fill (writefill_st1e),
.write_addr (writeaddr_st1e),
.write_data (use_write_data)
);
VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`BANK_LINE_SIZE_RNG*32) )) s0_1_c0 (
.clk (clk),
.reset(reset),
.stall(stall),
.flush(0),
.in ({qual_read_valid_st1, qual_read_dirty_st1, qual_read_tag_st1, qual_read_data_st1}),
.out ({read_valid_st1c[0] , read_dirty_st1c[0] , read_tag_st1c[0] , read_data_st1c[0]})
);
genvar curr_stage;
generate
for (curr_stage = 1; curr_stage < `STAGE_1_CYCLES; curr_stage = curr_stage + 1) begin
VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`BANK_LINE_SIZE_RNG*32) )) s0_1_cc (
.clk (clk),
.reset(reset),
.stall(stall),
.flush(0),
.in ({read_valid_st1c[curr_stage-1] , read_dirty_st1c[curr_stage-1] , read_tag_st1c[curr_stage-1] , read_data_st1c[curr_stage-1]})
.out ({read_valid_st1c[curr_stage] , read_dirty_st1c[curr_stage] , read_tag_st1c[curr_stage] , read_data_st1c[curr_stage] })
);
end
endgenerate
assign use_read_valid_st1e = read_valid_st1c[`STAGE_1_CYCLES-1];
assign use_read_dirty_st1e = read_dirty_st1c[`STAGE_1_CYCLES-1];
assign use_read_tag_st1e = read_tag_st1c [`STAGE_1_CYCLES-1];
assign use_read_data_st1e = read_data_st1c [`STAGE_1_CYCLES-1];
/////////////////////// LOAD LOGIC ///////////////////
wire[`OFFSET_SIZE_RNG] byte_select = writeaddr_st1e[`OFFSET_ADDR_RNG];
wire[`WORD_SELECT_SIZE_RNG] block_offset = writeaddr_st1e[`WORD_SELECT_ADDR_RNG];
wire lw = (mem_read_st1e == `LW_MEM_READ);
wire lb = (mem_read_st1e == `LB_MEM_READ);
wire lh = (mem_read_st1e == `LH_MEM_READ);
wire lhu = (mem_read_st1e == `LHU_MEM_READ);
wire lbu = (mem_read_st1e == `LBU_MEM_READ);
wire b0 = (byte_select == 0);
wire b1 = (byte_select == 1);
wire b2 = (byte_select == 2);
wire b3 = (byte_select == 3);
wire[31:0] data_unQual = (b0 || lw) ? (use_read_data_st1e[block_offset]) :
b1 ? (use_read_data_st1e[block_offset] >> 8) :
b2 ? (use_read_data_st1e[block_offset] >> 16) :
(use_read_data_st1e[block_offset] >> 24);
wire[31:0] lb_data = (data_unQual[7] ) ? (data_unQual | 32'hFFFFFF00) : (data_unQual & 32'hFF);
wire[31:0] lh_data = (data_unQual[15]) ? (data_unQual | 32'hFFFF0000) : (data_unQual & 32'hFFFF);
wire[31:0] lbu_data = (data_unQual & 32'hFF);
wire[31:0] lhu_data = (data_unQual & 32'hFFFF);
wire[31:0] lw_data = (data_unQual);
wire[31:0] sw_data = writedata_st1e;
wire[31:0] sb_data = b1 ? {{16{1'b0}}, writedata_st1e[7:0], { 8{1'b0}}} :
b2 ? {{ 8{1'b0}}, writedata_st1e[7:0], {16{1'b0}}} :
b3 ? {{ 0{1'b0}}, writedata_st1e[7:0], {24{1'b0}}} :
writedata_st1e;
wire[31:0] sh_data = b2 ? {writedata_st1e[15:0], {16{1'b0}}} : writedata_st1e;
wire[31:0] use_write_dat = sb ? sb_data :
sh ? sh_data :
sw_data;
wire[31:0] data_Qual = lb ? lb_data :
lh ? lh_data :
lhu ? lhu_data :
lbu ? lbu_data :
lw_data;
/////////////////////// STORE LOGIC ///////////////////
wire sw = (mem_write_st1e == `SW_MEM_WRITE);
wire sb = (mem_write_st1e == `SB_MEM_WRITE);
wire sh = (mem_write_st1e == `SH_MEM_WRITE);
wire[3:0] sb_mask = (b0 ? 4'b0001 : (b1 ? 4'b0010 : (b2 ? 4'b0100 : 4'b1000)));
wire[3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100);
wire should_write = (sw || sb || sh) && valid_req_st1e && !miss_st1e;
wire force_write = writefill_st1e && valid_req_st1e;
wire[`BANK_LINE_SIZE_RNG][3:0] we;
wire[`BANK_LINE_SIZE_RNG][31:0] data_write;
genvar g;
generate
for (g = 0; g < NUM_WORDS_PER_BLOCK; g = g + 1) begin : write_enables
wire normal_write = (block_offset == g) && should_write;
assign we[g] = (force_write) ? 4'b1111 :
(normal_write && sw) ? 4'b1111 :
(normal_write && sb) ? sb_mask :
(normal_write && sh) ? sh_mask :
4'b0000;
assign data_write[g] = force_write ? writedata_st1e : use_write_dat ;
end
endgenerate
assign use_write_enable = we;
assign use_write_data = data_write;
///////////////////////
assign readword_st1e = data_Qual;
assign miss_st1e = valid_req_st1e && use_read_valid_st1e && !writefill_st1e && (writeaddr_st1e[`TAG_SELECT_ADDR_RNG] != use_read_tag_st1e)
assign dirty_st1e = valid_req_st1e && use_read_valid_st1e && use_read_dirty_st1e;
assign readdata_st1e = use_read_data_st1e;
assign readtag_st1e = use_read_tag_st1e;
endmodule

52
rtl/VX_cache/VX_tag_data_structure.v
View File

@@ -1,15 +1,51 @@
module VX_tag_data_structure (
input wire clk,
input wire clk,
input wire reset,
input wire[31:0] readaddr,
output wire[`BANK_LINE_SIZE_RNG][31:0] readdata,
input wire[31:0] read_addr,
output wire read_valid,
output wire read_dirty,
output wire[`TAG_SELECT_SIZE_RNG] read_tag,
output wire[`BANK_LINE_SIZE_RNG][31:0] read_data,
input wire[`BANK_LINE_SIZE_RNG][3] writeenable,
input wire[31:0] writeaddr,
input wire[`BANK_LINE_SIZE_RNG][31:0] writedata
input wire[`BANK_LINE_SIZE_RNG][3:0] write_enable,
input wire write_fill,
input wire[31:0] write_addr,
input wire[`BANK_LINE_SIZE_RNG][31:0] write_data
);
endmodule
reg[`BANK_LINE_SIZE_RNG:0][3:0][7:0] data [`BANK_LINE_COUNT-1:0];
reg[`TAG_SELECT_SIZE_RNG] tag [`BANK_LINE_COUNT-1:0];
reg valid[`BANK_LINE_COUNT-1:0];
reg dirty[`BANK_LINE_COUNT-1:0];
// OFFSET_SIZE_RNG
assign read_valid <= valid[read_addr[`LINE_SELECT_ADDR_RNG]];
assign read_dirty <= dirty[read_addr[`LINE_SELECT_ADDR_RNG]];
assign read_tag <= tag [read_addr[`LINE_SELECT_ADDR_RNG]];
assign read_data <= data [read_addr[`LINE_SELECT_ADDR_RNG]];
wire going_to_write = (|write_enable);
always @(posedge clk) begin
if (going_to_write) begin
valid[write_addr[`LINE_SELECT_ADDR_RNG]] <= 1;
tag [write_addr[`LINE_SELECT_ADDR_RNG]] <= write_addr[`TAG_SELECT_ADDR_RNG];
if (write_fill) begin
dirty[write_addr[`LINE_SELECT_ADDR_RNG]] <= 0;
end else begin
dirty[write_addr[`LINE_SELECT_ADDR_RNG]] <= 1;
end
end
for (f = 0; f < `BANK_LINE_SIZE_WORDS; f = f + 1) begin
if (write_enable[f][0]) data[addr[`LINE_SELECT_ADDR_RNG]][f][0] <= data_write[f][7 :0 ];
if (write_enable[f][1]) data[addr[`LINE_SELECT_ADDR_RNG]][f][1] <= data_write[f][15:8 ];
if (write_enable[f][2]) data[addr[`LINE_SELECT_ADDR_RNG]][f][2] <= data_write[f][23:16];
if (write_enable[f][3]) data[addr[`LINE_SELECT_ADDR_RNG]][f][3] <= data_write[f][31:24];
end
end
endmodule