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Added Parameterization

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This commit is contained in:
Savan Roshan
2019-11-04 13:20:34 -05:00
parent a28a1c45c1
commit 8264339853
7 changed files with 609 additions and 578 deletions
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318
rtl/VX_define.v
View File

@@ -1,150 +1,168 @@
`define NT 4
`define NT_M1 (`NT-1)
// NW_M1 is actually log2(NW)
`define NW_M1 (3-1)
`define NW 8
// Uncomment the below line if NW=1
// `define ONLY
// `define SYN 1
`define ASIC 1
`define CACHE_NUM_BANKS 8
`define NUMBER_BANKS 8
`define NUM_WORDS_PER_BLOCK 4
`define NUM_BARRIERS 4
`define R_INST 7'd51
`define L_INST 7'd3
`define ALU_INST 7'd19
`define S_INST 7'd35
`define B_INST 7'd99
`define LUI_INST 7'd55
`define AUIPC_INST 7'd23
`define JAL_INST 7'd111
`define JALR_INST 7'd103
`define SYS_INST 7'd115
`define GPGPU_INST 7'h6b
`define WB_ALU 2'h1
`define WB_MEM 2'h2
`define WB_JAL 2'h3
`define NO_WB 2'h0
`define RS2_IMMED 1
`define RS2_REG 0
`define NO_MEM_READ 3'h7
`define LB_MEM_READ 3'h0
`define LH_MEM_READ 3'h1
`define LW_MEM_READ 3'h2
`define LBU_MEM_READ 3'h4
`define LHU_MEM_READ 3'h5
`define NO_MEM_WRITE 3'h7
`define SB_MEM_WRITE 3'h0
`define SH_MEM_WRITE 3'h1
`define SW_MEM_WRITE 3'h2
`define NO_BRANCH 3'h0
`define BEQ 3'h1
`define BNE 3'h2
`define BLT 3'h3
`define BGT 3'h4
`define BLTU 3'h5
`define BGTU 3'h6
`define NO_ALU 5'd15
`define ADD 5'd0
`define SUB 5'd1
`define SLLA 5'd2
`define SLT 5'd3
`define SLTU 5'd4
`define XOR 5'd5
`define SRL 5'd6
`define SRA 5'd7
`define OR 5'd8
`define AND 5'd9
`define SUBU 5'd10
`define LUI_ALU 5'd11
`define AUIPC_ALU 5'd12
`define CSR_ALU_RW 5'd13
`define CSR_ALU_RS 5'd14
`define CSR_ALU_RC 5'd15
`define MUL 5'd16
`define MULH 5'd17
`define MULHSU 5'd18
`define MULHU 5'd19
`define DIV 5'd20
`define DIVU 5'd21
`define REM 5'd22
`define REMU 5'd23
// WRITEBACK
`define WB_ALU 2'h1
`define WB_MEM 2'h2
`define WB_JAL 2'h3
`define NO_WB 2'h0
// JAL
`define JUMP 1'h1
`define NO_JUMP 1'h0
// STALLS
`define STALL 1'h1
`define NO_STALL 1'h0
`define TAKEN 1'b1
`define NOT_TAKEN 1'b0
`define ZERO_REG 5'h0
// `define PARAM
// Offset
`define CACHE_OFFSET_NB ($clog2(NUM_WORDS_PER_BLOCK))
`define CACHE_OFFSET_ST (2+$clog2(NUMBER_BANKS))
`define CACHE_OFFSET_ED (`CACHE_OFFSET_ST+(`CACHE_OFFSET_NB)-1)
`define CACHE_ADDR_OFFSET_RNG `CACHE_OFFSET_ED:`CACHE_OFFSET_ST
`define CACHE_OFFSET_SIZE_RNG ($clog2(NUM_WORDS_PER_BLOCK)-1):0
// Index
`define NUM_IND (CACHE_SIZE / (CACHE_WAYS * CACHE_BLOCK_PER_BANK))
`define CACHE_IND_NB ($clog2(`NUM_IND))
`define CACHE_IND_ST (`CACHE_OFFSET_ED+1)
`define CACHE_IND_ED (`CACHE_IND_ST+`CACHE_IND_NB-1)
`define CACHE_ADDR_IND_RNG `CACHE_IND_ED:`CACHE_IND_ST
`define CACHE_IND_SIZE_RNG `CACHE_IND_NB-1:0
// Tag
`define CACHE_ADDR_TAG_RNG 31:(`CACHE_IND_ED+1)
`define CACHE_TAG_SIZE_RNG (32-(`CACHE_IND_ED+1)-1):0
`define NT 4
`define NT_M1 (`NT-1)
// NW_M1 is actually log2(NW)
`define NW_M1 (3-1)
`define NW 8
// Uncomment the below line if NW=1
// `define ONLY
// `define SYN 1
`define ASIC 1
`define CACHE_NUM_BANKS 8
`define NUMBER_BANKS 8
`define NUM_WORDS_PER_BLOCK 4
`define NUM_BARRIERS 4
`define R_INST 7'd51
`define L_INST 7'd3
`define ALU_INST 7'd19
`define S_INST 7'd35
`define B_INST 7'd99
`define LUI_INST 7'd55
`define AUIPC_INST 7'd23
`define JAL_INST 7'd111
`define JALR_INST 7'd103
`define SYS_INST 7'd115
`define GPGPU_INST 7'h6b
`define WB_ALU 2'h1
`define WB_MEM 2'h2
`define WB_JAL 2'h3
`define NO_WB 2'h0
`define RS2_IMMED 1
`define RS2_REG 0
`define NO_MEM_READ 3'h7
`define LB_MEM_READ 3'h0
`define LH_MEM_READ 3'h1
`define LW_MEM_READ 3'h2
`define LBU_MEM_READ 3'h4
`define LHU_MEM_READ 3'h5
`define NO_MEM_WRITE 3'h7
`define SB_MEM_WRITE 3'h0
`define SH_MEM_WRITE 3'h1
`define SW_MEM_WRITE 3'h2
`define NO_BRANCH 3'h0
`define BEQ 3'h1
`define BNE 3'h2
`define BLT 3'h3
`define BGT 3'h4
`define BLTU 3'h5
`define BGTU 3'h6
`define NO_ALU 5'd15
`define ADD 5'd0
`define SUB 5'd1
`define SLLA 5'd2
`define SLT 5'd3
`define SLTU 5'd4
`define XOR 5'd5
`define SRL 5'd6
`define SRA 5'd7
`define OR 5'd8
`define AND 5'd9
`define SUBU 5'd10
`define LUI_ALU 5'd11
`define AUIPC_ALU 5'd12
`define CSR_ALU_RW 5'd13
`define CSR_ALU_RS 5'd14
`define CSR_ALU_RC 5'd15
`define MUL 5'd16
`define MULH 5'd17
`define MULHSU 5'd18
`define MULHU 5'd19
`define DIV 5'd20
`define DIVU 5'd21
`define REM 5'd22
`define REMU 5'd23
// WRITEBACK
`define WB_ALU 2'h1
`define WB_MEM 2'h2
`define WB_JAL 2'h3
`define NO_WB 2'h0
// JAL
`define JUMP 1'h1
`define NO_JUMP 1'h0
// STALLS
`define STALL 1'h1
`define NO_STALL 1'h0
`define TAKEN 1'b1
`define NOT_TAKEN 1'b0
`define ZERO_REG 5'h0
// `define PARAM
//Cache configurations
`define CACHE_SIZE 4096 //Bytes
`ifdef SYN
`define CACHE_WAYS 1
`else
`define CACHE_WAYS 2
`endif
`define CACHE_BLOCK 128 //Bytes
`define CACHE_BANKS 8
`define NUM_WORDS_PER_BLOCK 4
`define NUM_REQ `NT
`define CACHE_WAY_INDEX $clog2(`CACHE_WAYS) //set this to 1 if CACHE_WAYS is 1
//`define CACHE_WAY_INDEX 1
`define CACHE_BLOCK_PER_BANK (`CACHE_BLOCK / `CACHE_BANKS)
// Offset
`define CACHE_OFFSET_NB ($clog2(`NUM_WORDS_PER_BLOCK))
`define CACHE_OFFSET_ST (2+$clog2(`NUMBER_BANKS))
`define CACHE_OFFSET_ED (`CACHE_OFFSET_ST+(`CACHE_OFFSET_NB)-1)
`define CACHE_ADDR_OFFSET_RNG `CACHE_OFFSET_ED:`CACHE_OFFSET_ST
`define CACHE_OFFSET_SIZE_RNG ($clog2(`NUM_WORDS_PER_BLOCK)-1):0
// Index
`define NUM_IND (`CACHE_SIZE / (`CACHE_WAYS * `CACHE_BLOCK_PER_BANK))
`define CACHE_IND_NB ($clog2(`NUM_IND))
`define CACHE_IND_ST (`CACHE_OFFSET_ED+1)
`define CACHE_IND_ED (`CACHE_IND_ST+`CACHE_IND_NB-1)
`define CACHE_ADDR_IND_RNG `CACHE_IND_ED:`CACHE_IND_ST
`define CACHE_IND_SIZE_RNG `CACHE_IND_NB-1:0
// Tag
`define CACHE_ADDR_TAG_RNG 31:(`CACHE_IND_ED+1)
`define CACHE_TAG_SIZE_RNG (32-(`CACHE_IND_ED+1)-1):0

180
rtl/VX_dmem_controller.v
View File

@@ -1,91 +1,91 @@
`include "VX_define.v"
module VX_dmem_controller (
input wire clk,
input wire reset,
// MEM-RAM
VX_dram_req_rsp_inter VX_dram_req_rsp,
// MEM-Processor
VX_dcache_request_inter VX_dcache_req,
VX_dcache_response_inter VX_dcache_rsp
);
wire to_shm = VX_dcache_req.out_cache_driver_in_address[0][31:24] == 8'hFF;
wire[`NT_M1:0] sm_driver_in_valid = VX_dcache_req.out_cache_driver_in_valid & {`NT{to_shm}};
wire[`NT_M1:0] cache_driver_in_valid = VX_dcache_req.out_cache_driver_in_valid & {`NT{~to_shm}};
wire read_or_write = (VX_dcache_req.out_cache_driver_in_mem_write != `NO_MEM_WRITE) && (|cache_driver_in_valid);
wire[`NT_M1:0][31:0] cache_driver_in_address = VX_dcache_req.out_cache_driver_in_address;
wire[2:0] cache_driver_in_mem_read = !(|cache_driver_in_valid) ? `NO_MEM_READ : VX_dcache_req.out_cache_driver_in_mem_read;
wire[2:0] cache_driver_in_mem_write = !(|cache_driver_in_valid) ? `NO_MEM_WRITE : VX_dcache_req.out_cache_driver_in_mem_write;
wire[`NT_M1:0][31:0] cache_driver_in_data = VX_dcache_req.out_cache_driver_in_data;
wire[`NT_M1:0][31:0] cache_driver_out_data;
wire[`NT_M1:0][31:0] sm_driver_out_data;
wire[`NT_M1:0] cache_driver_out_valid; // Not used for now
wire sm_delay;
wire cache_delay;
wire valid_read_cache = !cache_delay && cache_driver_in_valid[0];
VX_shared_memory #(.NB(7), .BITS_PER_BANK(3)) shared_memory (
.clk (clk),
.reset (reset),
.in_valid (sm_driver_in_valid),
.in_address(cache_driver_in_address),
.in_data (cache_driver_in_data),
.mem_read (cache_driver_in_mem_read),
.mem_write (cache_driver_in_mem_write),
.out_valid (cache_driver_out_valid),
.out_data (sm_driver_out_data),
.stall (sm_delay)
);
VX_d_cache
#(
.CACHE_SIZE(4096), // Bytes
`ifdef SYN
.CACHE_WAYS(1),
`else
.CACHE_WAYS(2),
`endif
.CACHE_BLOCK(128), // Bytes
.CACHE_BANKS(8),
.NUM_REQ(`NT)
) dcache
(
.clk (clk),
.rst (reset),
.i_p_valid (cache_driver_in_valid),
.i_p_addr (cache_driver_in_address),
.i_p_writedata (cache_driver_in_data),
.i_p_read_or_write (read_or_write),
.i_p_mem_read (cache_driver_in_mem_read),
.i_p_mem_write (cache_driver_in_mem_write),
.o_p_readdata (cache_driver_out_data),
.o_p_delay (cache_delay),
.o_m_evict_addr (VX_dram_req_rsp.o_m_evict_addr),
.o_m_read_addr (VX_dram_req_rsp.o_m_read_addr),
.o_m_valid (VX_dram_req_rsp.o_m_valid),
.o_m_writedata (VX_dram_req_rsp.o_m_writedata),
.o_m_read_or_write (VX_dram_req_rsp.o_m_read_or_write),
.i_m_readdata (VX_dram_req_rsp.i_m_readdata),
.i_m_ready (VX_dram_req_rsp.i_m_ready)
);
assign VX_dcache_rsp.in_cache_driver_out_data = to_shm ? sm_driver_out_data : cache_driver_out_data;
assign VX_dcache_rsp.delay = sm_delay || cache_delay;
`include "VX_define.v"
module VX_dmem_controller (
input wire clk,
input wire reset,
// MEM-RAM
VX_dram_req_rsp_inter VX_dram_req_rsp,
// MEM-Processor
VX_dcache_request_inter VX_dcache_req,
VX_dcache_response_inter VX_dcache_rsp
);
wire to_shm = VX_dcache_req.out_cache_driver_in_address[0][31:24] == 8'hFF;
wire[`NT_M1:0] sm_driver_in_valid = VX_dcache_req.out_cache_driver_in_valid & {`NT{to_shm}};
wire[`NT_M1:0] cache_driver_in_valid = VX_dcache_req.out_cache_driver_in_valid & {`NT{~to_shm}};
wire read_or_write = (VX_dcache_req.out_cache_driver_in_mem_write != `NO_MEM_WRITE) && (|cache_driver_in_valid);
wire[`NT_M1:0][31:0] cache_driver_in_address = VX_dcache_req.out_cache_driver_in_address;
wire[2:0] cache_driver_in_mem_read = !(|cache_driver_in_valid) ? `NO_MEM_READ : VX_dcache_req.out_cache_driver_in_mem_read;
wire[2:0] cache_driver_in_mem_write = !(|cache_driver_in_valid) ? `NO_MEM_WRITE : VX_dcache_req.out_cache_driver_in_mem_write;
wire[`NT_M1:0][31:0] cache_driver_in_data = VX_dcache_req.out_cache_driver_in_data;
wire[`NT_M1:0][31:0] cache_driver_out_data;
wire[`NT_M1:0][31:0] sm_driver_out_data;
wire[`NT_M1:0] cache_driver_out_valid; // Not used for now
wire sm_delay;
wire cache_delay;
wire valid_read_cache = !cache_delay && cache_driver_in_valid[0];
VX_shared_memory #(.NB(7), .BITS_PER_BANK(3)) shared_memory (
.clk (clk),
.reset (reset),
.in_valid (sm_driver_in_valid),
.in_address(cache_driver_in_address),
.in_data (cache_driver_in_data),
.mem_read (cache_driver_in_mem_read),
.mem_write (cache_driver_in_mem_write),
.out_valid (cache_driver_out_valid),
.out_data (sm_driver_out_data),
.stall (sm_delay)
);
VX_d_cache
/*#(
.CACHE_SIZE(4096), // Bytes
`ifdef SYN
.CACHE_WAYS(1),
`else
.CACHE_WAYS(2),
`endif
.CACHE_BLOCK(128), // Bytes
.CACHE_BANKS(8),
.NUM_REQ(`NT)
)*/ dcache
(
.clk (clk),
.rst (reset),
.i_p_valid (cache_driver_in_valid),
.i_p_addr (cache_driver_in_address),
.i_p_writedata (cache_driver_in_data),
.i_p_read_or_write (read_or_write),
.i_p_mem_read (cache_driver_in_mem_read),
.i_p_mem_write (cache_driver_in_mem_write),
.o_p_readdata (cache_driver_out_data),
.o_p_delay (cache_delay),
.o_m_evict_addr (VX_dram_req_rsp.o_m_evict_addr),
.o_m_read_addr (VX_dram_req_rsp.o_m_read_addr),
.o_m_valid (VX_dram_req_rsp.o_m_valid),
.o_m_writedata (VX_dram_req_rsp.o_m_writedata),
.o_m_read_or_write (VX_dram_req_rsp.o_m_read_or_write),
.i_m_readdata (VX_dram_req_rsp.i_m_readdata),
.i_m_ready (VX_dram_req_rsp.i_m_ready)
);
assign VX_dcache_rsp.in_cache_driver_out_data = to_shm ? sm_driver_out_data : cache_driver_out_data;
assign VX_dcache_rsp.delay = sm_delay || cache_delay;
endmodule

37
rtl/cache/VX_Cache_Bank.v vendored
View File

@@ -7,12 +7,12 @@
module VX_Cache_Bank
#(
/*#(
parameter CACHE_SIZE = 4096, // Bytes
parameter CACHE_WAYS = 1,
parameter CACHE_BLOCK = 128, // Bytes
parameter CACHE_BANKS = 8
)
)*/
(
clk,
rst,
@@ -42,10 +42,10 @@ module VX_Cache_Bank
way_use
);
localparam NUMBER_BANKS = CACHE_BANKS;
localparam CACHE_BLOCK_PER_BANK = (CACHE_BLOCK / CACHE_BANKS);
localparam NUM_WORDS_PER_BLOCK = CACHE_BLOCK / (CACHE_BANKS*4);
localparam NUMBER_INDEXES = `NUM_IND;
// localparam NUMBER_BANKS = `CACHE_BANKS;
// localparam CACHE_BLOCK_PER_BANK = (`CACHE_BLOCK / `CACHE_BANKS);
// localparam NUM_WORDS_PER_BLOCK = `CACHE_BLOCK / (`CACHE_BANKS*4);
// localparam NUMBER_INDEXES = `NUM_IND;
localparam CACHE_IDLE = 0; // Idle
localparam SEND_MEM_REQ = 1; // Write back this block into memory
@@ -69,14 +69,14 @@ module VX_Cache_Bank
input wire valid_in;
input wire read_or_write; // Specifies if it is a read or write operation
input wire[NUM_WORDS_PER_BLOCK-1:0][31:0] fetched_writedata;
input wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] fetched_writedata;
input wire[2:0] i_p_mem_read;
input wire[2:0] i_p_mem_write;
input wire[1:0] byte_select;
input wire[$clog2(CACHE_WAYS)-1:0] evicted_way;
output wire[$clog2(CACHE_WAYS)-1:0] way_use;
input wire[`CACHE_WAY_INDEX-1:0] evicted_way;
output wire[`CACHE_WAY_INDEX-1:0] way_use;
// Outputs
// Normal shit
@@ -89,11 +89,11 @@ module VX_Cache_Bank
output wire[31:0] eviction_addr; // What's the eviction tag
// Eviction Data (Extraction)
output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_evicted;
output wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_evicted;
wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use;
wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_use;
wire[`CACHE_TAG_SIZE_RNG] tag_use;
wire[`CACHE_TAG_SIZE_RNG] eviction_tag;
wire valid_use;
@@ -104,8 +104,8 @@ module VX_Cache_Bank
wire[$clog2(CACHE_WAYS)-1:0] update_way;
wire[$clog2(CACHE_WAYS)-1:0] way_to_update;
wire[`CACHE_WAY_INDEX-1:0] update_way;
wire[`CACHE_WAY_INDEX-1:0] way_to_update;
assign miss = (tag_use != o_tag) && valid_use && valid_in;
@@ -180,10 +180,10 @@ module VX_Cache_Bank
wire[3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100);
wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we;
wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write;
wire[`NUM_WORDS_PER_BLOCK-1:0][3:0] we;
wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_write;
genvar g;
for (g = 0; g < NUM_WORDS_PER_BLOCK; g = g + 1) begin
for (g = 0; g < `NUM_WORDS_PER_BLOCK; g = g + 1) begin
wire normal_write = (read_or_write && ((access && (block_offset == g))) && !miss);
assign we[g] = (write_from_mem) ? 4'b1111 :
@@ -199,12 +199,13 @@ module VX_Cache_Bank
end
VX_cache_data_per_index #(
/*VX_cache_data_per_index #(
.CACHE_SIZE(CACHE_SIZE),
.CACHE_WAYS(CACHE_WAYS),
.CACHE_BLOCK(CACHE_BLOCK),
.CACHE_BANKS(CACHE_BANKS),
.NUM_WORDS_PER_BLOCK(NUM_WORDS_PER_BLOCK)) data_structures(
.NUM_WORDS_PER_BLOCK(NUM_WORDS_PER_BLOCK)) data_structures(*/
VX_cache_data_per_index data_structures(
.clk (clk),
.rst (rst),
.valid_in (valid_in),

462
rtl/cache/VX_cache_data.v vendored
View File

@@ -1,231 +1,231 @@
`include "../VX_define.v"
module VX_cache_data
#(
parameter CACHE_SIZE = 4096, // Bytes
parameter CACHE_WAYS = 1,
parameter CACHE_BLOCK = 128, // Bytes
parameter CACHE_BANKS = 8,
parameter NUM_WORDS_PER_BLOCK = 4
)
(
input wire clk, rst, // Clock
// `ifdef PARAM
// Addr
input wire[`CACHE_IND_SIZE_RNG] addr,
// WE
input wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we,
input wire evict,
// Data
input wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write,
input wire[`CACHE_TAG_SIZE_RNG] tag_write,
output wire[`CACHE_TAG_SIZE_RNG] tag_use,
output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use,
output wire valid_use,
output wire dirty_use
// `else
// // Addr
// input wire[7:0] addr,
// // WE
// input wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we,
// input wire evict,
// // Data
// input wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write, // Update Data
// input wire[16:0] tag_write,
// output wire[16:0] tag_use,
// output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use,
// output wire valid_use,
// output wire dirty_use
// `endif
);
localparam NUMBER_BANKS = CACHE_BANKS;
localparam CACHE_BLOCK_PER_BANK = (CACHE_BLOCK / CACHE_BANKS);
// localparam NUM_WORDS_PER_BLOCK = CACHE_BLOCK / (CACHE_BANKS*4);
localparam NUMBER_INDEXES = `NUM_IND;
wire currently_writing = (|we);
wire update_dirty = ((!dirty_use) && currently_writing) || (evict);
wire dirt_new = evict ? 0 : (|we);
`ifndef SYN
// (3:0) 4 bytes
reg[NUM_WORDS_PER_BLOCK-1:0][3:0][7:0] data[NUMBER_INDEXES-1:0]; // Actual Data
reg[`CACHE_TAG_SIZE_RNG] tag[NUMBER_INDEXES-1:0];
reg valid[NUMBER_INDEXES-1:0];
reg dirty[NUMBER_INDEXES-1:0];
// 16 bytes
assign data_use = data[addr]; // Read Port
assign tag_use = tag[addr];
assign valid_use = valid[addr];
assign dirty_use = dirty[addr];
integer f;
integer ini_ind;
always @(posedge clk, posedge rst) begin : update_all
if (rst) begin
for (ini_ind = 0; ini_ind < NUMBER_INDEXES; ini_ind=ini_ind+1) begin
data[ini_ind] <= 0;
tag[ini_ind] <= 0;
valid[ini_ind] <= 0;
dirty[ini_ind] <= 0;
end
end else begin
if (update_dirty) dirty[addr] <= dirt_new; // WRite Port
if (evict) tag[addr] <= tag_write;
if (evict) valid[addr] <= 1;
for (f = 0; f < NUM_WORDS_PER_BLOCK; f = f + 1) begin
if (we[f][0]) data[addr][f][0] <= data_write[f][7 :0 ];
if (we[f][1]) data[addr][f][1] <= data_write[f][15:8 ];
if (we[f][2]) data[addr][f][2] <= data_write[f][23:16];
if (we[f][3]) data[addr][f][3] <= data_write[f][31:24];
end
end
end
`else
wire cena = 1;
wire cenb_d = (|we);
wire[NUM_WORDS_PER_BLOCK-1:0][31:0] wdata_d = data_write;
wire[NUM_WORDS_PER_BLOCK-1:0][31:0] write_bit_mask_d;
wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_out_d;
genvar cur_b;
for (cur_b = 0; cur_b < NUM_WORDS_PER_BLOCK; cur_b=cur_b+1) begin
assign write_bit_mask_d[cur_b] = {32{~we[cur_b]}};
end
assign data_use = data_out_d;
// Using ASIC MEM
/* verilator lint_off PINCONNECTEMPTY */
rf2_256x128_wm1 data (
.CENYA(),
.AYA(),
.CENYB(),
.WENYB(),
.AYB(),
.QA(data_out_d),
.SOA(),
.SOB(),
.CLKA(clk),
.CENA(cena),
.AA(addr),
.CLKB(clk),
.CENB(cenb_d),
.WENB(write_bit_mask_d),
.AB(addr),
.DB(wdata_d),
.EMAA(3'b011),
.EMASA(1'b0),
.EMAB(3'b011),
.TENA(1'b1),
.TCENA(1'b0),
.TAA(8'b0),
.TENB(1'b1),
.TCENB(1'b0),
.TWENB(128'b0),
.TAB(8'b0),
.TDB(128'b0),
.RET1N(1'b1),
.SIA(2'b0),
.SEA(1'b0),
.DFTRAMBYP(1'b0),
.SIB(2'b0),
.SEB(1'b0),
.COLLDISN(1'b1)
);
/* verilator lint_on PINCONNECTEMPTY */
wire[16:0] old_tag;
wire old_valid;
wire old_dirty;
wire[16:0] new_tag = evict ? tag_write : old_tag;
wire new_valid = evict ? 1 : old_valid;
wire new_dirty = update_dirty ? dirt_new : old_dirty;
wire cenb_m = (evict || update_dirty);
wire[19-1:0][31:0] write_bit_mask_m = cenb_m ? 19'b0 : 19'b1;
// Try to fix the error in memory conneciton, modified by Lingjun Zhu on Oct. 28 2019
// wire[NUM_WORDS_PER_BLOCK-1:0][31:0] wdata_m = {new_tag, new_dirty, new_valid};
// wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_out_m;
wire[19-1:0] wdata_m = {new_tag, new_dirty, new_valid};
wire[19-1:0] data_out_m;
assign {old_tag, old_dirty, old_valid} = data_out_m;
assign dirty_use = old_dirty;
assign valid_use = old_valid;
assign tag_use = old_tag;
/* verilator lint_off PINCONNECTEMPTY */
rf2_256x19_wm0 meta (
.CENYA(),
.AYA(),
.CENYB(),
// .WENYB(),
.AYB(),
.QA(data_out_m),
.SOA(),
.SOB(),
.CLKA(clk),
.CENA(cena),
.AA(addr),
.CLKB(clk),
.CENB(cenb_m),
// .WENB(write_bit_mask_m),
.AB(addr),
.DB(wdata_m),
.EMAA(3'b011),
.EMASA(1'b0),
.EMAB(3'b011),
.TENA(1'b1),
.TCENA(1'b0),
.TAA(8'b0),
.TENB(1'b1),
.TCENB(1'b0),
// .TWENB(128'b0),
.TAB(8'b0),
.TDB(19'b0),
.RET1N(1'b1),
.SIA(2'b0),
.SEA(1'b0),
.DFTRAMBYP(1'b0),
.SIB(2'b0),
.SEB(1'b0),
.COLLDISN(1'b1)
);
/* verilator lint_on PINCONNECTEMPTY */
`endif
endmodule
`include "../VX_define.v"
module VX_cache_data
/*#(
parameter CACHE_SIZE = 4096, // Bytes
parameter CACHE_WAYS = 1,
parameter CACHE_BLOCK = 128, // Bytes
parameter CACHE_BANKS = 8,
parameter NUM_WORDS_PER_BLOCK = 4
)*/
(
input wire clk, rst, // Clock
// `ifdef PARAM
// Addr
input wire[`CACHE_IND_SIZE_RNG] addr,
// WE
input wire[`NUM_WORDS_PER_BLOCK-1:0][3:0] we,
input wire evict,
// Data
input wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_write,
input wire[`CACHE_TAG_SIZE_RNG] tag_write,
output wire[`CACHE_TAG_SIZE_RNG] tag_use,
output wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_use,
output wire valid_use,
output wire dirty_use
// `else
// // Addr
// input wire[7:0] addr,
// // WE
// input wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we,
// input wire evict,
// // Data
// input wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write, // Update Data
// input wire[16:0] tag_write,
// output wire[16:0] tag_use,
// output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use,
// output wire valid_use,
// output wire dirty_use
// `endif
);
//localparam NUMBER_BANKS = CACHE_BANKS;
//localparam CACHE_BLOCK_PER_BANK = (CACHE_BLOCK / CACHE_BANKS);
// localparam NUM_WORDS_PER_BLOCK = CACHE_BLOCK / (CACHE_BANKS*4);
//localparam NUMBER_INDEXES = `NUM_IND;
wire currently_writing = (|we);
wire update_dirty = ((!dirty_use) && currently_writing) || (evict);
wire dirt_new = evict ? 0 : (|we);
`ifndef SYN
// (3:0) 4 bytes
reg[`NUM_WORDS_PER_BLOCK-1:0][3:0][7:0] data[`NUM_IND-1:0]; // Actual Data
reg[`CACHE_TAG_SIZE_RNG] tag[`NUM_IND-1:0];
reg valid[`NUM_IND-1:0];
reg dirty[`NUM_IND-1:0];
// 16 bytes
assign data_use = data[addr]; // Read Port
assign tag_use = tag[addr];
assign valid_use = valid[addr];
assign dirty_use = dirty[addr];
integer f;
integer ini_ind;
always @(posedge clk, posedge rst) begin : update_all
if (rst) begin
for (ini_ind = 0; ini_ind < `NUM_IND; ini_ind=ini_ind+1) begin
data[ini_ind] <= 0;
tag[ini_ind] <= 0;
valid[ini_ind] <= 0;
dirty[ini_ind] <= 0;
end
end else begin
if (update_dirty) dirty[addr] <= dirt_new; // WRite Port
if (evict) tag[addr] <= tag_write;
if (evict) valid[addr] <= 1;
for (f = 0; f < `NUM_WORDS_PER_BLOCK; f = f + 1) begin
if (we[f][0]) data[addr][f][0] <= data_write[f][7 :0 ];
if (we[f][1]) data[addr][f][1] <= data_write[f][15:8 ];
if (we[f][2]) data[addr][f][2] <= data_write[f][23:16];
if (we[f][3]) data[addr][f][3] <= data_write[f][31:24];
end
end
end
`else
wire cena = 1;
wire cenb_d = (|we);
wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] wdata_d = data_write;
wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] write_bit_mask_d;
wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_out_d;
genvar cur_b;
for (cur_b = 0; cur_b < `NUM_WORDS_PER_BLOCK; cur_b=cur_b+1) begin
assign write_bit_mask_d[cur_b] = {32{~we[cur_b]}};
end
assign data_use = data_out_d;
// Using ASIC MEM
/* verilator lint_off PINCONNECTEMPTY */
rf2_256x128_wm1 data (
.CENYA(),
.AYA(),
.CENYB(),
.WENYB(),
.AYB(),
.QA(data_out_d),
.SOA(),
.SOB(),
.CLKA(clk),
.CENA(cena),
.AA(addr),
.CLKB(clk),
.CENB(cenb_d),
.WENB(write_bit_mask_d),
.AB(addr),
.DB(wdata_d),
.EMAA(3'b011),
.EMASA(1'b0),
.EMAB(3'b011),
.TENA(1'b1),
.TCENA(1'b0),
.TAA(8'b0),
.TENB(1'b1),
.TCENB(1'b0),
.TWENB(128'b0),
.TAB(8'b0),
.TDB(128'b0),
.RET1N(1'b1),
.SIA(2'b0),
.SEA(1'b0),
.DFTRAMBYP(1'b0),
.SIB(2'b0),
.SEB(1'b0),
.COLLDISN(1'b1)
);
/* verilator lint_on PINCONNECTEMPTY */
wire[16:0] old_tag;
wire old_valid;
wire old_dirty;
wire[16:0] new_tag = evict ? tag_write : old_tag;
wire new_valid = evict ? 1 : old_valid;
wire new_dirty = update_dirty ? dirt_new : old_dirty;
wire cenb_m = (evict || update_dirty);
wire[19-1:0][31:0] write_bit_mask_m = cenb_m ? 19'b0 : 19'b1;
// Try to fix the error in memory conneciton, modified by Lingjun Zhu on Oct. 28 2019
// wire[NUM_WORDS_PER_BLOCK-1:0][31:0] wdata_m = {new_tag, new_dirty, new_valid};
// wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_out_m;
wire[19-1:0] wdata_m = {new_tag, new_dirty, new_valid};
wire[19-1:0] data_out_m;
assign {old_tag, old_dirty, old_valid} = data_out_m;
assign dirty_use = old_dirty;
assign valid_use = old_valid;
assign tag_use = old_tag;
/* verilator lint_off PINCONNECTEMPTY */
rf2_256x19_wm0 meta (
.CENYA(),
.AYA(),
.CENYB(),
// .WENYB(),
.AYB(),
.QA(data_out_m),
.SOA(),
.SOB(),
.CLKA(clk),
.CENA(cena),
.AA(addr),
.CLKB(clk),
.CENB(cenb_m),
// .WENB(write_bit_mask_m),
.AB(addr),
.DB(wdata_m),
.EMAA(3'b011),
.EMASA(1'b0),
.EMAB(3'b011),
.TENA(1'b1),
.TCENA(1'b0),
.TAA(8'b0),
.TENB(1'b1),
.TCENB(1'b0),
// .TWENB(128'b0),
.TAB(8'b0),
.TDB(19'b0),
.RET1N(1'b1),
.SIA(2'b0),
.SEA(1'b0),
.DFTRAMBYP(1'b0),
.SIB(2'b0),
.SEB(1'b0),
.COLLDISN(1'b1)
);
/* verilator lint_on PINCONNECTEMPTY */
`endif
endmodule

91
rtl/cache/VX_cache_data_per_index.v vendored
View File

@@ -3,13 +3,13 @@
`include "../VX_define.v"
module VX_cache_data_per_index
#(
/*#(
parameter CACHE_SIZE = 4096, // Bytes
parameter CACHE_WAYS = 1,
parameter CACHE_BLOCK = 128, // Bytes
parameter CACHE_BANKS = 8,
parameter NUM_WORDS_PER_BLOCK = CACHE_BLOCK / (CACHE_BANKS*4)
)
)*/
(
input wire clk, // Clock
input wire rst,
@@ -17,52 +17,62 @@ module VX_cache_data_per_index
// Addr
input wire[`CACHE_IND_SIZE_RNG] addr,
// WE
input wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we,
input wire[`NUM_WORDS_PER_BLOCK-1:0][3:0] we,
input wire evict,
input wire[$clog2(CACHE_WAYS)-1:0] way_to_update,
input wire[`CACHE_WAY_INDEX-1:0] way_to_update,
// Data
input wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write, // Update Data
input wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_write, // Update Data
input wire[`CACHE_TAG_SIZE_RNG] tag_write,
output wire[`CACHE_TAG_SIZE_RNG] tag_use,
output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use,
output wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_use,
output wire valid_use,
output wire dirty_use,
output wire[$clog2(CACHE_WAYS)-1:0] way
output wire[`CACHE_WAY_INDEX-1:0] way
);
localparam NUMBER_BANKS = CACHE_BANKS;
localparam CACHE_BLOCK_PER_BANK = (CACHE_BLOCK / CACHE_BANKS);
//localparam NUMBER_BANKS = CACHE_BANKS;
//localparam CACHE_BLOCK_PER_BANK = (CACHE_BLOCK / CACHE_BANKS);
// localparam NUM_WORDS_PER_BLOCK = CACHE_BLOCK / (CACHE_BANKS*4);
localparam NUMBER_INDEXES = `NUM_IND;
//localparam NUMBER_INDEXES = `NUM_IND;
wire [CACHE_WAYS-1:0][`CACHE_TAG_SIZE_RNG] tag_use_per_way;
wire [CACHE_WAYS-1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] data_use_per_way;
wire [CACHE_WAYS-1:0] valid_use_per_way;
wire [CACHE_WAYS-1:0] dirty_use_per_way;
wire [CACHE_WAYS-1:0] hit_per_way;
reg [NUMBER_INDEXES-1:0][$clog2(CACHE_WAYS)-1:0] eviction_way_index;
wire [CACHE_WAYS-1:0][NUM_WORDS_PER_BLOCK-1:0][3:0] we_per_way;
wire [CACHE_WAYS-1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] data_write_per_way;
wire [CACHE_WAYS-1:0] write_from_mem_per_way;
wire [`CACHE_WAYS-1:0][`CACHE_TAG_SIZE_RNG] tag_use_per_way;
wire [`CACHE_WAYS-1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] data_use_per_way;
wire [`CACHE_WAYS-1:0] valid_use_per_way;
wire [`CACHE_WAYS-1:0] dirty_use_per_way;
wire [`CACHE_WAYS-1:0] hit_per_way;
reg [`NUM_IND-1:0][`CACHE_WAY_INDEX-1:0] eviction_way_index;
wire [`CACHE_WAYS-1:0][`NUM_WORDS_PER_BLOCK-1:0][3:0] we_per_way;
wire [`CACHE_WAYS-1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] data_write_per_way;
wire [`CACHE_WAYS-1:0] write_from_mem_per_way;
wire invalid_found;
wire [$clog2(CACHE_WAYS)-1:0] way_index;
wire [$clog2(CACHE_WAYS)-1:0] invalid_index;
VX_generic_priority_encoder #(.N(CACHE_WAYS)) valid_index
(
.valids(~valid_use_per_way),
.index (invalid_index),
.found (invalid_found)
);
wire [`CACHE_WAY_INDEX-1:0] way_index;
wire [`CACHE_WAY_INDEX-1:0] invalid_index;
if(`CACHE_WAYS != 1) begin
VX_generic_priority_encoder #(.N(`CACHE_WAYS)) valid_index
(
.valids(~valid_use_per_way),
.index (invalid_index),
.found (invalid_found)
);
VX_generic_priority_encoder #(.N(`CACHE_WAYS)) way_indexing
(
.valids(hit_per_way),
.index (way_index),
.found ()
);
end
else begin
assign way_index = 0;
assign invalid_found = (valid_use_per_way == 1'b0) ? 1 : 0;
assign invalid_index = 0;
end
VX_generic_priority_encoder #(.N(CACHE_WAYS)) way_indexing
(
.valids(hit_per_way),
.index (way_index),
.found ()
);
@@ -80,18 +90,19 @@ module VX_cache_data_per_index
genvar ways;
for(ways=0; ways < CACHE_WAYS; ways = ways + 1) begin
for(ways=0; ways < `CACHE_WAYS; ways = ways + 1) begin
assign hit_per_way[ways] = ((valid_use_per_way[ways] == 1'b1) && (tag_use_per_way[ways] == tag_write)) ? 1'b1 : 0;
assign we_per_way[ways] = (evict == 1'b1) || (update == 1'b1) ? ((ways == way_to_update) ? (we) : 0) : 0;
assign data_write_per_way[ways] = (evict == 1'b1) || (update == 1'b1) ? ((ways == way_to_update) ? data_write : 0) : 0;
assign write_from_mem_per_way[ways] = (evict == 1'b1) ? ((ways == way_to_update) ? 1 : 0) : 0;
VX_cache_data #(
.CACHE_SIZE(CACHE_SIZE),
.CACHE_WAYS(CACHE_WAYS),
.CACHE_BLOCK(CACHE_BLOCK),
.CACHE_BANKS(CACHE_BANKS)) data_structures(
/*VX_cache_data #(
.CACHE_SIZE(`CACHE_SIZE),
.CACHE_WAYS(`CACHE_WAYS),
.CACHE_BLOCK(`CACHE_BLOCK),
.CACHE_BANKS(`CACHE_BANKS)) data_structures(*/
VX_cache_data data_structures(
.clk (clk),
.rst (rst),
// Inputs
@@ -113,7 +124,7 @@ module VX_cache_data_per_index
eviction_way_index <= 0;
end else begin
if(miss && dirty_use && valid_use && !evict && valid_in) begin // can be either evict or invalid cache entries
if((eviction_way_index[addr]+1) == CACHE_WAYS) begin
if((eviction_way_index[addr]+1) == `CACHE_WAYS) begin
eviction_way_index[addr] <= 0;
end else begin
eviction_way_index[addr] <= (eviction_way_index[addr] + 1);

96
rtl/cache/VX_d_cache.v vendored
View File

@@ -14,13 +14,13 @@
//`include "cache_set.v"
module VX_d_cache
#(
/*#(
parameter CACHE_SIZE = 4096, // Bytes
parameter CACHE_WAYS = 1,
parameter CACHE_BLOCK = 128, // Bytes
parameter CACHE_BANKS = 8,
parameter NUM_REQ = 8
)
)*/
(
clk,
rst,
@@ -47,10 +47,10 @@ module VX_d_cache
i_m_ready
);
parameter NUMBER_BANKS = CACHE_BANKS;
localparam NUM_WORDS_PER_BLOCK = CACHE_BLOCK / (CACHE_BANKS*4);
//parameter NUMBER_BANKS = `CACHE_BANKS;
//localparam NUM_WORDS_PER_BLOCK = `CACHE_BLOCK / (`CACHE_BANKS*4);
localparam CACHE_BLOCK_PER_BANK = (CACHE_BLOCK / NUMBER_BANKS);
//localparam CACHE_BLOCK_PER_BANK = (`CACHE_BLOCK / `CACHE_BANKS);
localparam CACHE_IDLE = 0; // Idle
localparam SEND_MEM_REQ = 1; // Write back this block into memory
@@ -59,18 +59,18 @@ module VX_d_cache
//parameter cache_entry = 9;
input wire clk, rst;
input wire [NUM_REQ-1:0] i_p_valid;
input wire [NUM_REQ-1:0][31:0] i_p_addr; // FIXME
input wire [NUM_REQ-1:0][31:0] i_p_writedata;
input wire [`NUM_REQ-1:0] i_p_valid;
input wire [`NUM_REQ-1:0][31:0] i_p_addr; // FIXME
input wire [`NUM_REQ-1:0][31:0] i_p_writedata;
input wire i_p_read_or_write; //, i_p_write;
output reg [NUM_REQ-1:0][31:0] o_p_readdata;
output reg [`NUM_REQ-1:0][31:0] o_p_readdata;
output wire o_p_delay;
output reg [31:0] o_m_evict_addr; // Address is xxxxxxxxxxoooobbbyy
output reg [31:0] o_m_read_addr;
output reg o_m_valid;
output reg[NUMBER_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata;
output reg[`CACHE_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata;
output reg o_m_read_or_write; //, o_m_write;
input wire[NUMBER_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata;
input wire[`CACHE_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata;
input wire i_m_ready;
input wire[2:0] i_p_mem_read;
@@ -78,41 +78,41 @@ module VX_d_cache
// Buffer for final data
reg [NUM_REQ-1:0][31:0] final_data_read;
reg [NUM_REQ-1:0][31:0] new_final_data_read;
wire[NUM_REQ-1:0][31:0] new_final_data_read_Qual;
reg [`NUM_REQ-1:0][31:0] final_data_read;
reg [`NUM_REQ-1:0][31:0] new_final_data_read;
wire[`NUM_REQ-1:0][31:0] new_final_data_read_Qual;
assign o_p_readdata = new_final_data_read_Qual;
wire[NUMBER_BANKS - 1 : 0][NUM_REQ-1:0] thread_track_banks; // Valid thread mask per bank
wire[NUMBER_BANKS - 1 : 0][$clog2(NUM_REQ)-1:0] index_per_bank; // Index of thread each bank will try to service
wire[NUMBER_BANKS - 1 : 0][NUM_REQ-1:0] use_mask_per_bank; // A mask of index_per_bank
wire[NUMBER_BANKS - 1 : 0] valid_per_bank; // Valid request going to each bank
wire[NUMBER_BANKS - 1 : 0][NUM_REQ-1:0] threads_serviced_per_bank; // Bank successfully serviced per bank
wire[`CACHE_BANKS - 1 : 0][`NUM_REQ-1:0] thread_track_banks; // Valid thread mask per bank
wire[`CACHE_BANKS - 1 : 0][$clog2(`NUM_REQ)-1:0] index_per_bank; // Index of thread each bank will try to service
wire[`CACHE_BANKS - 1 : 0][`NUM_REQ-1:0] use_mask_per_bank; // A mask of index_per_bank
wire[`CACHE_BANKS - 1 : 0] valid_per_bank; // Valid request going to each bank
wire[`CACHE_BANKS - 1 : 0][`NUM_REQ-1:0] threads_serviced_per_bank; // Bank successfully serviced per bank
wire[NUMBER_BANKS-1:0][31:0] readdata_per_bank; // Data read from each bank
wire[NUMBER_BANKS-1:0] hit_per_bank; // Whether each bank got a hit or a miss
wire[NUMBER_BANKS-1:0] eviction_wb;
reg[NUMBER_BANKS-1:0] eviction_wb_old;
wire[`CACHE_BANKS-1:0][31:0] readdata_per_bank; // Data read from each bank
wire[`CACHE_BANKS-1:0] hit_per_bank; // Whether each bank got a hit or a miss
wire[`CACHE_BANKS-1:0] eviction_wb;
reg[`CACHE_BANKS-1:0] eviction_wb_old;
wire[NUMBER_BANKS -1 : 0][$clog2(CACHE_WAYS)-1:0] evicted_way_new;
reg [NUMBER_BANKS -1 : 0][$clog2(CACHE_WAYS)-1:0] evicted_way_old;
wire[NUMBER_BANKS -1 : 0][$clog2(CACHE_WAYS)-1:0] way_used;
wire[`CACHE_BANKS -1 : 0][`CACHE_WAY_INDEX-1:0] evicted_way_new;
reg [`CACHE_BANKS -1 : 0][`CACHE_WAY_INDEX-1:0] evicted_way_old;
wire[`CACHE_BANKS -1 : 0][`CACHE_WAY_INDEX-1:0] way_used;
// Internal State
reg [3:0] state;
wire[3:0] new_state;
wire[NUM_REQ-1:0] use_valid; // Valid used throught the code
reg[NUM_REQ-1:0] stored_valid; // Saving the threads still left (bank conflict or bank miss)
wire[NUM_REQ-1:0] new_stored_valid; // New stored valid
wire[`NUM_REQ-1:0] use_valid; // Valid used throught the code
reg[`NUM_REQ-1:0] stored_valid; // Saving the threads still left (bank conflict or bank miss)
wire[`NUM_REQ-1:0] new_stored_valid; // New stored valid
reg[NUMBER_BANKS - 1 : 0][31:0] eviction_addr_per_bank;
reg[`CACHE_BANKS - 1 : 0][31:0] eviction_addr_per_bank;
reg[31:0] miss_addr;
reg[31:0] evict_addr;
@@ -127,39 +127,39 @@ module VX_d_cache
VX_cache_bank_valid #(.NUMBER_BANKS(NUMBER_BANKS)) multip_banks(
VX_cache_bank_valid #(.NUMBER_BANKS(`CACHE_BANKS)) multip_banks(
.i_p_valid (use_valid),
.i_p_addr (i_p_addr),
.thread_track_banks(thread_track_banks)
);
reg[NUM_REQ-1:0] threads_serviced_Qual;
reg[`NUM_REQ-1:0] threads_serviced_Qual;
reg[NUM_REQ-1:0] debug_hit_per_bank_mask[NUMBER_BANKS-1:0];
reg[`NUM_REQ-1:0] debug_hit_per_bank_mask[`CACHE_BANKS-1:0];
genvar bid;
for (bid = 0; bid < NUMBER_BANKS; bid=bid+1)
for (bid = 0; bid < `CACHE_BANKS; bid=bid+1)
begin
wire[NUM_REQ-1:0] use_threads_track_banks = thread_track_banks[bid];
wire[$clog2(NUM_REQ)-1:0] use_thread_index = index_per_bank[bid];
wire[`NUM_REQ-1:0] use_threads_track_banks = thread_track_banks[bid];
wire[$clog2(`NUM_REQ)-1:0] use_thread_index = index_per_bank[bid];
wire use_write_final_data = hit_per_bank[bid];
wire[31:0] use_data_final_data = readdata_per_bank[bid];
VX_priority_encoder_w_mask #(.N(NUM_REQ)) choose_thread(
VX_priority_encoder_w_mask #(.N(`NUM_REQ)) choose_thread(
.valids(use_threads_track_banks),
.mask (use_mask_per_bank[bid]),
.index (index_per_bank[bid]),
.found (valid_per_bank[bid])
);
assign debug_hit_per_bank_mask[bid] = {NUM_REQ{hit_per_bank[bid]}};
assign debug_hit_per_bank_mask[bid] = {`NUM_REQ{hit_per_bank[bid]}};
assign threads_serviced_per_bank[bid] = use_mask_per_bank[bid] & debug_hit_per_bank_mask[bid];
end
integer test_bid;
always @(*) begin
new_final_data_read = 0;
for (test_bid=0; test_bid < NUMBER_BANKS; test_bid=test_bid+1)
for (test_bid=0; test_bid < `CACHE_BANKS; test_bid=test_bid+1)
begin
if (hit_per_bank[test_bid]) begin
new_final_data_read[index_per_bank[test_bid]] = readdata_per_bank[test_bid];
@@ -168,7 +168,7 @@ module VX_d_cache
end
wire[NUMBER_BANKS - 1 : 0] detect_bank_miss;
wire[`CACHE_BANKS - 1 : 0] detect_bank_miss;
assign threads_serviced_Qual = threads_serviced_per_bank[0] | threads_serviced_per_bank[1] |
threads_serviced_per_bank[2] | threads_serviced_per_bank[3] |
threads_serviced_per_bank[4] | threads_serviced_per_bank[5] |
@@ -184,7 +184,7 @@ module VX_d_cache
genvar tid;
for (tid = 0; tid < NUM_REQ; tid =tid+1)
for (tid = 0; tid < `NUM_REQ; tid =tid+1)
begin
assign new_final_data_read_Qual[tid] = threads_serviced_Qual[tid] ? new_final_data_read[tid] : final_data_read[tid];
end
@@ -197,12 +197,12 @@ module VX_d_cache
assign o_p_delay = delay;
wire[NUMBER_BANKS - 1 : 0][$clog2(NUM_REQ)-1:0] send_index_to_bank = index_per_bank;
wire[`CACHE_BANKS - 1 : 0][$clog2(`NUM_REQ)-1:0] send_index_to_bank = index_per_bank;
wire[$clog2(NUMBER_BANKS)-1:0] miss_bank_index;
wire[`CACHE_WAY_INDEX-1:0] miss_bank_index;
wire miss_found;
VX_generic_priority_encoder #(.N(NUMBER_BANKS)) get_miss_index
VX_generic_priority_encoder #(.N(`CACHE_BANKS)) get_miss_index
(
.valids(detect_bank_miss),
.index (miss_bank_index),
@@ -258,7 +258,7 @@ module VX_d_cache
genvar bank_id;
generate
for (bank_id = 0; bank_id < NUMBER_BANKS; bank_id = bank_id + 1)
for (bank_id = 0; bank_id < `CACHE_BANKS; bank_id = bank_id + 1)
begin
wire[31:0] bank_addr = (state == SEND_MEM_REQ) ? evict_addr :
(state == RECIV_MEM_RSP) ? miss_addr :
@@ -280,12 +280,12 @@ module VX_d_cache
((state == SEND_MEM_REQ)) ? 1'b0 :
normal_valid_in;
VX_Cache_Bank #(
/*VX_Cache_Bank #(
.CACHE_SIZE(CACHE_SIZE),
.CACHE_WAYS(CACHE_WAYS),
.CACHE_BLOCK(CACHE_BLOCK),
.CACHE_BANKS(CACHE_BANKS)) bank_structure
(
.CACHE_BANKS(CACHE_BANKS)) bank_structure*/
VX_Cache_Bank bank_structure(
.clk (clk),
.rst (rst),
.state (state),

3
rtl/modelsim/vortex_tb.v
View File

@@ -61,7 +61,8 @@ module vortex_tb (
initial begin
// $fdumpfile("vortex1.vcd");
load_file("../../runtime/vortex_runtime.hex");
//load_file("../../runtime/vortex_runtime.hex");
load_file("../../kernel/vortex_test.hex");
$dumpvars(0, vortex_tb);
reset = 1;
clk = 0;