add tensor core memory interface

hw/rtl/VX_config.vh

@@ -83,7 +83,7 @@
 `endif
 
 `ifndef NUM_CORES
-`define NUM_CORES 8
+`define NUM_CORES 4
 `endif
 
 `ifndef NUM_WARPS

hw/rtl/VX_core_wrapper.sv

@@ -74,6 +74,14 @@ module Vortex import VX_gpu_pkg::*; #(
     output [(DCACHE_NUM_REQS * 4) - 1:0]                     smem_a_bits_mask,
     output [(DCACHE_NUM_REQS * 32) - 1:0]                    smem_a_bits_data,
 
+    // tc --------------------------------------------------
+    input  [1:0]   tc_a_ready,
+    output [1:0]   tc_a_valid,
+    output [63:0]  tc_a_bits_address,
+    input  [511:0] tc_d_bits_data,
+    output [1:0]   tc_d_ready,
+    input  [1:0]   tc_d_valid,
+
     // gbar ------------------------------------------------
 
     output                   gbar_req_valid,
@@ -289,6 +297,19 @@ module Vortex import VX_gpu_pkg::*; #(
         end
     endgenerate
 
+    // tc ---------------------------------------------------------------------
+    VX_tc_bus_if tc_p0_bus_if();
+    VX_tc_bus_if tc_p1_bus_if();
+    assign tc_a_valid = {tc_p1_bus_if.req_valid, tc_p0_bus_if.req_valid};
+    assign tc_a_bits_address = {tc_p1_bus_if.req_data, tc_p0_bus_if.req_data};
+    assign tc_p0_bus_if.req_ready = tc_a_ready[0];
+    assign tc_p0_bus_if.rsp_valid = tc_d_valid[0];
+    assign tc_p0_bus_if.rsp_data = tc_d_bits_data[0];
+    assign tc_p1_bus_if.req_ready = tc_a_ready[1];
+    assign tc_p1_bus_if.rsp_valid = tc_d_valid[1];
+    assign tc_p1_bus_if.rsp_data = tc_d_bits_data[1];
+    assign tc_d_ready = {tc_p1_bus_if.rsp_ready, tc_p0_bus_if.rsp_ready};
+
     // gbar -------------------------------------------------------------------
 `ifdef GBAR_ENABLE
     VX_gbar_bus_if gbar_bus_if();
@@ -420,6 +441,9 @@ module Vortex import VX_gpu_pkg::*; #(
         .gbar_bus_if    (gbar_bus_if),
     `endif
 
+        .tc_p0_bus_if   (tc_p0_bus_if),
+        .tc_p1_bus_if   (tc_p1_bus_if),
+
         .sim_ebreak     (sim_ebreak),
         .sim_wb_value   (sim_wb_value),
         .busy           (busy),

hw/rtl/VX_platform.vh

@@ -33,7 +33,7 @@
 
 `ifdef SYNTHESIS
 `define NUM_BARRIERS 8
-`define NUM_CORES 8
+`define NUM_CORES 4
 `define NUM_THREADS 8
 `define NUM_WARPS 8
 

hw/rtl/core/VX_core.sv

@@ -39,6 +39,9 @@ module VX_core import VX_gpu_pkg::*; #(
 
     VX_mem_bus_if.master    icache_bus_if,
 
+    VX_tc_bus_if.master     tc_p0_bus_if,
+    VX_tc_bus_if.master     tc_p1_bus_if,
+
 `ifdef GBAR_ENABLE
     VX_gbar_bus_if.master   gbar_bus_if,
 `endif

hw/rtl/mem/VX_tc_bus_if.sv

@@ -0,0 +1,57 @@
+// Copyright © 2019-2023
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// http://www.apache.org/licenses/LICENSE-2.0
+// 
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+`include "VX_define.vh"
+
+interface VX_tc_bus_if #(
+    parameter DATA_SIZE  = 32,
+    parameter ADDR_WIDTH = `MEM_ADDR_WIDTH
+)();
+
+    typedef struct packed {
+        logic [ADDR_WIDTH-1:0] addr;
+    } req_data_t;
+
+    typedef struct packed {
+        logic [DATA_SIZE*8-1:0] data;
+    } rsp_data_t;
+
+    logic  req_valid;
+    req_data_t req_data;
+    logic  req_ready;
+
+    logic  rsp_valid;
+    rsp_data_t rsp_data;
+    logic  rsp_ready;
+
+    modport master (
+        output req_valid,
+        output req_data,
+        input  req_ready,
+
+        input  rsp_valid,
+        input  rsp_data,
+        output rsp_ready
+    );
+
+    modport slave (
+        input  req_valid,
+        input  req_data,
+        output req_ready,
+
+        output rsp_valid,
+        output rsp_data,
+        input  rsp_ready
+    );
+
+endinterface