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simx: add cycle and core id to load/store memory debug trace

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This commit is contained in:
Hansung Kim
2023-02-17 18:31:29 -08:00
parent d81e4085e2
commit 9cf5a29917
1 changed files with 27 additions and 5 deletions
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32
sim/simx/execute.cpp
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@@ -690,8 +690,13 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
uint64_t mem_addr = rsdata[t][0].i + immsrc; uint64_t mem_addr = rsdata[t][0].i + immsrc;
uint64_t mem_data = 0; uint64_t mem_data = 0;
core_->dcache_read(&mem_data, mem_addr, mem_bytes); core_->dcache_read(&mem_data, mem_addr, mem_bytes);
trace->mem_addrs.at(t).push_back({mem_addr, mem_bytes}); trace->mem_addrs.at(t).push_back({mem_addr, mem_bytes});
DP(4, "LOAD MEM: THREAD=" << t << ", ADDRESS=0x" << std::hex << mem_addr << ", DATA=0x" << mem_data << std::dec << ", BYTES=" << mem_bytes); DP(1, "LOAD MEM: CYCLE=" << SimPlatform::instance().cycles()
<< ", CORE=" << core_->id()
<< ", THREAD=" << t
<< ", ADDRESS=0x" << std::hex << mem_addr
<< ", DATA=0x" << mem_data << std::dec
<< ", BYTES=" << mem_bytes);
switch (func3) { switch (func3) {
case 0: case 0:
// RV32I: LB // RV32I: LB
@@ -731,7 +736,13 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
core_->dcache_read(&mem_data, mem_addr, 4); core_->dcache_read(&mem_data, mem_addr, 4);
Word *result_ptr = (Word *)(vd.data() + i); Word *result_ptr = (Word *)(vd.data() + i);
*result_ptr = mem_data; *result_ptr = mem_data;
DP(4, "LOAD MEM: VLEN=" << vl_ << ", VID=" << i << ", ADDRESS=0x" << std::hex << mem_addr << ", DATA=0x" << mem_data << std::dec << ", BYTES=" << 4); DP(1, "LOAD MEM: CYCLE=" << SimPlatform::instance().cycles()
<< ", CORE=" << core_->id()
<< ", VLEN=" << vl_
<< ", VID=" << i
<< ", ADDRESS=0x" << std::hex << mem_addr
<< ", DATA=0x" << mem_data << std::dec
<< ", BYTES=" << 4);
} }
break; break;
} }
@@ -762,7 +773,12 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
mem_data &= mask; mem_data &= mask;
} }
trace->mem_addrs.at(t).push_back({mem_addr, mem_bytes}); trace->mem_addrs.at(t).push_back({mem_addr, mem_bytes});
DP(4, "STORE MEM: THREAD=" << t << ", ADDRESS=0x" << std::hex << mem_addr << ", DATA=0x" << mem_data << std::dec << ", BYTES=" << mem_bytes); DP(1, "STORE MEM: CYCLE=" << SimPlatform::instance().cycles()
<< ", CORE=" << core_->id()
<< ", THREAD=" << t
<< ", ADDRESS=0x" << std::hex << mem_addr
<< ", DATA=0x" << mem_data << std::dec
<< ", BYTES=" << mem_bytes);
switch (func3) { switch (func3) {
case 0: case 0:
case 1: case 1:
@@ -782,7 +798,13 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
// store word and unit strided (not checking for unit stride) // store word and unit strided (not checking for unit stride)
uint32_t mem_data = *(uint32_t *)(vreg_file_.at(instr.getVs3()).data() + i); uint32_t mem_data = *(uint32_t *)(vreg_file_.at(instr.getVs3()).data() + i);
core_->dcache_write(&mem_data, mem_addr, 4); core_->dcache_write(&mem_data, mem_addr, 4);
DP(4, "STORE MEM: VLEN=" << vl_ << ", VID=" << i << ", ADDRESS=0x" << std::hex << mem_addr << ", DATA=0x" << mem_data << std::dec << ", BYTES=" << 4); DP(1, "STORE MEM: CYCLE=" << SimPlatform::instance().cycles()
<< ", CORE=" << core_->id()
<< ", VLEN=" << vl_
<< ", VID=" << i
<< ", ADDRESS=0x" << std::hex << mem_addr
<< ", DATA=0x" << mem_data << std::dec
<< ", BYTES=" << 4);
break; break;
} }
default: default: