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simx: add thread ID and vlen to load/store memory debug trace

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This commit is contained in:
Hansung Kim
2023-02-17 17:59:56 -08:00
parent b9d1684582
commit d81e4085e2
3 changed files with 7 additions and 7 deletions
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2
sim/simx/core.cpp
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@@ -683,4 +683,4 @@ bool Core::check_exit() const {
bool Core::running() const {
bool is_running = (committed_instrs_ != issued_instrs_);
return is_running;
}
}

10
sim/simx/execute.cpp
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@@ -691,7 +691,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
uint64_t mem_data = 0;
core_->dcache_read(&mem_data, mem_addr, mem_bytes);
trace->mem_addrs.at(t).push_back({mem_addr, mem_bytes});
DP(4, "LOAD MEM: ADDRESS=0x" << std::hex << mem_addr << ", DATA=0x" << mem_data);
DP(4, "LOAD MEM: THREAD=" << t << ", ADDRESS=0x" << std::hex << mem_addr << ", DATA=0x" << mem_data << std::dec << ", BYTES=" << mem_bytes);
switch (func3) {
case 0:
// RV32I: LB
@@ -731,7 +731,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
core_->dcache_read(&mem_data, mem_addr, 4);
Word *result_ptr = (Word *)(vd.data() + i);
*result_ptr = mem_data;
DP(4, "LOAD MEM: ADDRESS=0x" << std::hex << mem_addr << ", DATA=0x" << mem_data);
DP(4, "LOAD MEM: VLEN=" << vl_ << ", VID=" << i << ", ADDRESS=0x" << std::hex << mem_addr << ", DATA=0x" << mem_data << std::dec << ", BYTES=" << 4);
}
break;
}
@@ -762,7 +762,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
mem_data &= mask;
}
trace->mem_addrs.at(t).push_back({mem_addr, mem_bytes});
DP(4, "STORE MEM: ADDRESS=0x" << std::hex << mem_addr << ", DATA=0x" << mem_data);
DP(4, "STORE MEM: THREAD=" << t << ", ADDRESS=0x" << std::hex << mem_addr << ", DATA=0x" << mem_data << std::dec << ", BYTES=" << mem_bytes);
switch (func3) {
case 0:
case 1:
@@ -782,7 +782,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
// store word and unit strided (not checking for unit stride)
uint32_t mem_data = *(uint32_t *)(vreg_file_.at(instr.getVs3()).data() + i);
core_->dcache_write(&mem_data, mem_addr, 4);
DP(4, "STORE MEM: ADDRESS=0x" << std::hex << mem_addr << ", DATA=0x" << mem_data);
DP(4, "STORE MEM: VLEN=" << vl_ << ", VID=" << i << ", ADDRESS=0x" << std::hex << mem_addr << ", DATA=0x" << mem_data << std::dec << ", BYTES=" << 4);
break;
}
default:
@@ -2349,4 +2349,4 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
DP(3, "*** Next PC: " << std::hex << nextPC << std::dec);
PC_ = nextPC;
}
}
}

2
sim/simx/processor.cpp
View File

@@ -175,4 +175,4 @@ void Processor::attach_ram(RAM* mem) {
int Processor::run() {
return impl_->run();
}
}