cache_sim.cpp created
This commit is contained in:
trmontgomery
42
hw/unit_tests/cache/Makefile
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42
hw/unit_tests/cache/Makefile
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@@ -0,0 +1,42 @@
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PARAM +=
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# control RTL debug print states
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DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \
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-DDBG_PRINT_CORE_DCACHE \
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-DDBG_PRINT_CACHE_BANK \
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-DDBG_PRINT_CACHE_SNP \
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-DDBG_PRINT_CACHE_MSRQ \
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-DDBG_PRINT_DRAM \
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-DDBG_PRINT_OPAE
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#DBG_PRINT=$(DBG_PRINT_FLAGS)
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INCLUDE = -I../../rtl/ -I../../rtl/cache -I../../rtl/libs
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SRCS = cache_sim.cpp
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all: build
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CF += -std=c++11 -fms-extensions -I../..
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VF += --language 1800-2009 --assert -Wall --trace #-Wpedantic
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VF += -Wno-DECLFILENAME
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VF += --x-initial unique
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VF += -exe $(SRCS) $(INCLUDE)
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DBG += -DVCD_OUTPUT $(DBG_PRINT)
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gen:
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verilator $(VF) -DNDEBUG -cc VX_cache.v $(PARAM) -CFLAGS '$(CF) -DNDEBUG $(PARAM)' --exe $(SRCS)
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build: gen
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(cd obj_dir && make -j -f VVX_cache.mk)
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run: build
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(cd obj_dir && ./VVX_cache)
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clean:
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rm -rf obj_dir
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74
hw/unit_tests/cache/cache_sim.cpp
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74
hw/unit_tests/cache/cache_sim.cpp
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@@ -0,0 +1,74 @@
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#include "VVX_cache.h"
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#include "VVX_cache__Syms.h"
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#include "verilated.h"
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#include <verilated_vcd_c.h>
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#include <iostream>
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#include <vector>
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uint64_t timestamp = 0;
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double sc_time_stamp() {
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return timestamp;
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}
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void tick(VVX_cache* tb){
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tb->eval();
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tb->clk = 1;
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tb->eval();
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tb->clk = 0;
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tb->eval();
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}
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int main(int argc, char **argv){
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Verilated::commandArgs(argc, argv); //passes the command args to the object
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VVX_cache *tb = new VVX_cachee;
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//reset the cache
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tb->reset = 1;
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tb->eval();
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tb->reset = 0;
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//declare variables for output - data members in cache class
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unsigned int clk;
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bool full;
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bool empty;
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int size;
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int data_out;
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//assign inputs
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tb->core_req_valid = 1;
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tb->core_req_rw = 1;
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char byte_en[] = {}; //word size 4 bytes
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tb->core_req_byteen[0] = 1;
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tb->core_req_byteen[1] = 1;
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tb->core_req_byteen[2] = 1;
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tb->core_req_byteen[3] = 1;
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char addr[4] = {0x1a, 0x2b, 0x3c, 0x4d}; //word addr width
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tb->core_req_addr[0] = arr[0];
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tb->core_req_addr[0] = arr[1];
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tb->core_req_addr[0] = arr[2];
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tb->core_req_addr[0] = arr[3];
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//char req_data[] = {}; //word width
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//tb->core_req_data
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//char req_tag[] = {}; //core_req_tag_count by core req_tag_width
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//tb->core_req_tag =
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for (int i = 0; i < 5; ++i){
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//toggle the clock
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tick(tb);
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}
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delete tb;
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exit(0);
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}
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0
hw/unit_tests/cache/cache_sim.h
vendored
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0
hw/unit_tests/cache/cache_sim.h
vendored
Normal file
56983
hw/unit_tests/cache/obj_dir/VVX_cache.cpp
vendored
Normal file
56983
hw/unit_tests/cache/obj_dir/VVX_cache.cpp
vendored
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File diff suppressed because it is too large
Load Diff
1681
hw/unit_tests/cache/obj_dir/VVX_cache.h
vendored
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1681
hw/unit_tests/cache/obj_dir/VVX_cache.h
vendored
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File diff suppressed because it is too large
Load Diff
67
hw/unit_tests/cache/obj_dir/VVX_cache.mk
vendored
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67
hw/unit_tests/cache/obj_dir/VVX_cache.mk
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@@ -0,0 +1,67 @@
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# Verilated -*- Makefile -*-
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# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
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#
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# Execute this makefile from the object directory:
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# make -f VVX_cache.mk
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default: VVX_cache
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### Constants...
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# Perl executable (from $PERL)
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PERL = perl
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# Path to Verilator kit (from $VERILATOR_ROOT)
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VERILATOR_ROOT = /usr/local/share/verilator
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# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
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SYSTEMC_INCLUDE ?=
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# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
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SYSTEMC_LIBDIR ?=
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### Switches...
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# SystemC output mode? 0/1 (from --sc)
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VM_SC = 0
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# Legacy or SystemC output mode? 0/1 (from --sc)
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VM_SP_OR_SC = $(VM_SC)
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# Deprecated
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VM_PCLI = 1
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# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH)
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VM_SC_TARGET_ARCH = linux
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### Vars...
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# Design prefix (from --prefix)
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VM_PREFIX = VVX_cache
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# Module prefix (from --prefix)
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VM_MODPREFIX = VVX_cache
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# User CFLAGS (from -CFLAGS on Verilator command line)
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VM_USER_CFLAGS = \
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-std=c++11 -fms-extensions -I../.. -DNDEBUG -DDATAW=4 -DSIZE=4 \
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# User LDLIBS (from -LDFLAGS on Verilator command line)
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VM_USER_LDLIBS = \
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# User .cpp files (from .cpp's on Verilator command line)
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VM_USER_CLASSES = \
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cache_sim \
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# User .cpp directories (from .cpp's on Verilator command line)
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VM_USER_DIR = \
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. \
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### Default rules...
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# Include list of all generated classes
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include VVX_cache_classes.mk
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# Include global rules
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include $(VERILATOR_ROOT)/include/verilated.mk
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### Executable rules... (from --exe)
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VPATH += $(VM_USER_DIR)
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cache_sim.o: cache_sim.cpp
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$(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
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### Link rules... (from --exe)
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VVX_cache: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a
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$(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) $(SC_LIBS)
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# Verilated -*- Makefile -*-
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||||
107
hw/unit_tests/cache/obj_dir/VVX_cache__Syms.cpp
vendored
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107
hw/unit_tests/cache/obj_dir/VVX_cache__Syms.cpp
vendored
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@@ -0,0 +1,107 @@
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// Verilated -*- C++ -*-
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// DESCRIPTION: Verilator output: Symbol table implementation internals
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#include "VVX_cache__Syms.h"
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#include "VVX_cache.h"
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// FUNCTIONS
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VVX_cache__Syms::VVX_cache__Syms(VVX_cache* topp, const char* namep)
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// Setup locals
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: __Vm_namep(namep)
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, __Vm_activity(false)
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, __Vm_didInit(false)
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// Setup submodule names
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{
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// Pointer to top level
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TOPp = topp;
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// Setup each module's pointers to their submodules
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// Setup each module's pointer back to symbol table (for public functions)
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TOPp->__Vconfigure(this, true);
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// Setup scopes
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__Vscope_VX_cache__cache_dram_req_arb__dram_fill_arb__dfqq_queue.configure(this, name(), "VX_cache.cache_dram_req_arb.dram_fill_arb.dfqq_queue", "dfqq_queue", VerilatedScope::SCOPE_OTHER);
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__Vscope_VX_cache__cache_dram_req_arb__dram_fill_arb__dfqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.cache_dram_req_arb.dram_fill_arb.dfqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
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__Vscope_VX_cache__cache_dram_req_arb__prfqq__pfq_queue.configure(this, name(), "VX_cache.cache_dram_req_arb.prfqq.pfq_queue", "pfq_queue", VerilatedScope::SCOPE_OTHER);
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__Vscope_VX_cache__cache_dram_req_arb__prfqq__pfq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.cache_dram_req_arb.prfqq.pfq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
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__Vscope_VX_cache__genblk5__BRA__0__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[0].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER);
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__Vscope_VX_cache__genblk5__BRA__0__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[0].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
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__Vscope_VX_cache__genblk5__BRA__0__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[0].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER);
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__Vscope_VX_cache__genblk5__BRA__0__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[0].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
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__Vscope_VX_cache__genblk5__BRA__0__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[0].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER);
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__Vscope_VX_cache__genblk5__BRA__0__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[0].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
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__Vscope_VX_cache__genblk5__BRA__0__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[0].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER);
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__Vscope_VX_cache__genblk5__BRA__0__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[0].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
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__Vscope_VX_cache__genblk5__BRA__0__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[0].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER);
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__Vscope_VX_cache__genblk5__BRA__0__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[0].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
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__Vscope_VX_cache__genblk5__BRA__1__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[1].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER);
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||||
__Vscope_VX_cache__genblk5__BRA__1__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[1].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__1__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[1].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__1__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[1].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__1__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[1].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__1__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[1].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__1__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[1].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__1__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[1].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__1__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[1].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__1__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[1].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__2__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[2].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__2__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[2].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__2__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[2].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__2__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[2].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__2__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[2].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__2__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[2].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__2__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[2].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__2__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[2].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__2__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[2].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__2__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[2].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__3__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[3].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__3__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[3].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__3__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[3].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__3__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[3].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__3__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[3].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__3__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[3].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__3__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[3].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__3__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[3].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__3__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[3].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__3__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[3].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__4__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[4].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__4__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[4].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__4__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[4].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__4__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[4].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__4__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[4].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__4__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[4].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__4__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[4].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__4__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[4].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__4__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[4].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__4__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[4].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__5__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[5].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__5__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[5].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__5__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[5].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__5__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[5].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__5__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[5].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__5__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[5].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__5__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[5].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__5__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[5].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__5__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[5].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__5__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[5].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__6__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[6].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__6__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[6].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__6__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[6].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__6__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[6].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__6__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[6].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__6__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[6].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__6__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[6].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__6__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[6].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__6__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[6].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__6__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[6].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__7__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[7].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__7__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[7].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__7__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[7].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__7__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[7].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__7__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[7].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__7__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[7].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__7__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[7].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__7__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[7].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__7__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[7].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER);
|
||||
__Vscope_VX_cache__genblk5__BRA__7__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[7].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
|
||||
}
|
||||
123
hw/unit_tests/cache/obj_dir/VVX_cache__Syms.h
vendored
Normal file
123
hw/unit_tests/cache/obj_dir/VVX_cache__Syms.h
vendored
Normal file
@@ -0,0 +1,123 @@
|
||||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Symbol table internal header
|
||||
//
|
||||
// Internal details; most calling programs do not need this header,
|
||||
// unless using verilator public meta comments.
|
||||
|
||||
#ifndef _VVX_CACHE__SYMS_H_
|
||||
#define _VVX_CACHE__SYMS_H_ // guard
|
||||
|
||||
#include "verilated_heavy.h"
|
||||
|
||||
// INCLUDE MODULE CLASSES
|
||||
#include "VVX_cache.h"
|
||||
|
||||
// SYMS CLASS
|
||||
class VVX_cache__Syms : public VerilatedSyms {
|
||||
public:
|
||||
|
||||
// LOCAL STATE
|
||||
const char* __Vm_namep;
|
||||
bool __Vm_activity; ///< Used by trace routines to determine change occurred
|
||||
bool __Vm_didInit;
|
||||
|
||||
// SUBCELL STATE
|
||||
VVX_cache* TOPp;
|
||||
|
||||
// SCOPE NAMES
|
||||
VerilatedScope __Vscope_VX_cache__cache_dram_req_arb__dram_fill_arb__dfqq_queue;
|
||||
VerilatedScope __Vscope_VX_cache__cache_dram_req_arb__dram_fill_arb__dfqq_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__cache_dram_req_arb__prfqq__pfq_queue;
|
||||
VerilatedScope __Vscope_VX_cache__cache_dram_req_arb__prfqq__pfq_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__core_req_arb__reqq_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__cwb_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__cwb_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__dfp_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__dfp_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__dwb_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__dwb_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__snp_req_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__snp_req_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__core_req_arb__reqq_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__cwb_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__cwb_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__dfp_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__dfp_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__dwb_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__dwb_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__snp_req_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__snp_req_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__core_req_arb__reqq_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__cwb_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__cwb_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__dfp_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__dfp_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__dwb_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__dwb_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__snp_req_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__snp_req_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__core_req_arb__reqq_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__cwb_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__cwb_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__dfp_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__dfp_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__dwb_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__dwb_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__snp_req_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__snp_req_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__core_req_arb__reqq_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__cwb_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__cwb_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__dfp_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__dfp_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__dwb_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__dwb_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__snp_req_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__snp_req_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__core_req_arb__reqq_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__cwb_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__cwb_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__dfp_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__dfp_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__dwb_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__dwb_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__snp_req_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__snp_req_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__core_req_arb__reqq_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__cwb_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__cwb_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__dfp_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__dfp_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__dwb_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__dwb_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__snp_req_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__snp_req_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__core_req_arb__reqq_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__cwb_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__cwb_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__dfp_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__dfp_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__dwb_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__dwb_queue__genblk3__genblk2;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__snp_req_queue;
|
||||
VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__snp_req_queue__genblk3__genblk2;
|
||||
|
||||
// CREATORS
|
||||
VVX_cache__Syms(VVX_cache* topp, const char* namep);
|
||||
~VVX_cache__Syms() {}
|
||||
|
||||
// METHODS
|
||||
inline const char* name() { return __Vm_namep; }
|
||||
inline bool getClearActivity() { bool r=__Vm_activity; __Vm_activity=false; return r; }
|
||||
|
||||
} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES);
|
||||
|
||||
#endif // guard
|
||||
9560
hw/unit_tests/cache/obj_dir/VVX_cache__Trace.cpp
vendored
Normal file
9560
hw/unit_tests/cache/obj_dir/VVX_cache__Trace.cpp
vendored
Normal file
File diff suppressed because it is too large
Load Diff
15246
hw/unit_tests/cache/obj_dir/VVX_cache__Trace__Slow.cpp
vendored
Normal file
15246
hw/unit_tests/cache/obj_dir/VVX_cache__Trace__Slow.cpp
vendored
Normal file
File diff suppressed because it is too large
Load Diff
43
hw/unit_tests/cache/obj_dir/VVX_cache_classes.mk
vendored
Normal file
43
hw/unit_tests/cache/obj_dir/VVX_cache_classes.mk
vendored
Normal file
@@ -0,0 +1,43 @@
|
||||
# Verilated -*- Makefile -*-
|
||||
# DESCRIPTION: Verilator output: Make include file with class lists
|
||||
#
|
||||
# This file lists generated Verilated files, for including in higher level makefiles.
|
||||
# See VVX_cache.mk for the caller.
|
||||
|
||||
### Switches...
|
||||
# Coverage output mode? 0/1 (from --coverage)
|
||||
VM_COVERAGE = 0
|
||||
# Threaded output mode? 0/1/N threads (from --threads)
|
||||
VM_THREADS = 0
|
||||
# Tracing output mode? 0/1 (from --trace)
|
||||
VM_TRACE = 1
|
||||
# Tracing threaded output mode? 0/1 (from --trace-fst-thread)
|
||||
VM_TRACE_THREADED = 0
|
||||
|
||||
### Object file lists...
|
||||
# Generated module classes, fast-path, compile with highest optimization
|
||||
VM_CLASSES_FAST += \
|
||||
VVX_cache \
|
||||
|
||||
# Generated module classes, non-fast-path, compile with low/medium optimization
|
||||
VM_CLASSES_SLOW += \
|
||||
|
||||
# Generated support classes, fast-path, compile with highest optimization
|
||||
VM_SUPPORT_FAST += \
|
||||
VVX_cache__Trace \
|
||||
|
||||
# Generated support classes, non-fast-path, compile with low/medium optimization
|
||||
VM_SUPPORT_SLOW += \
|
||||
VVX_cache__Syms \
|
||||
VVX_cache__Trace__Slow \
|
||||
|
||||
# Global classes, need linked once per executable, fast-path, compile with highest optimization
|
||||
VM_GLOBAL_FAST += \
|
||||
verilated \
|
||||
verilated_vcd_c \
|
||||
|
||||
# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization
|
||||
VM_GLOBAL_SLOW += \
|
||||
|
||||
|
||||
# Verilated -*- Makefile -*-
|
||||
83
hw/unit_tests/cache/simulator.cpp
vendored
Normal file
83
hw/unit_tests/cache/simulator.cpp
vendored
Normal file
@@ -0,0 +1,83 @@
|
||||
#include "simulator.h"
|
||||
#include <iostream>
|
||||
#include <fstream>
|
||||
#include <iomanip>
|
||||
|
||||
uint64_t timestamp = 0;
|
||||
|
||||
double sc_time_stamp() {
|
||||
return timestamp;
|
||||
}
|
||||
|
||||
Simulator::Simulator() {
|
||||
// force random values for unitialized signals
|
||||
Verilated::randReset(1);
|
||||
|
||||
vortex_ = new VVX_priority_encoder();
|
||||
|
||||
#ifdef VCD_OUTPUT
|
||||
Verilated::traceEverOn(true);
|
||||
trace_ = new VerilatedVcdC;
|
||||
vortex_->trace(trace_, 99);
|
||||
trace_->open("trace.vcd");
|
||||
#endif
|
||||
}
|
||||
|
||||
Simulator::~Simulator() {
|
||||
#ifdef VCD_OUTPUT
|
||||
trace_->close();
|
||||
#endif
|
||||
delete vortex_;
|
||||
}
|
||||
|
||||
|
||||
|
||||
void Simulator::step() {
|
||||
this->eval();
|
||||
|
||||
this->eval();
|
||||
}
|
||||
|
||||
|
||||
void Simulator::reset() {
|
||||
#ifndef NDEBUG
|
||||
std::cout << timestamp << ": [sim] reset()" << std::endl;
|
||||
#endif
|
||||
|
||||
this->step();
|
||||
}
|
||||
|
||||
|
||||
void Simulator::eval() {
|
||||
vortex_->eval();
|
||||
#ifdef VCD_OUTPUT
|
||||
trace_->dump(timestamp);
|
||||
#endif
|
||||
++timestamp;
|
||||
}
|
||||
|
||||
void Simulator::wait(uint32_t cycles) {
|
||||
for (int i = 0; i < cycles; ++i) {
|
||||
this->step();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
bool Simulator::run() {
|
||||
// reset the device
|
||||
this->reset();
|
||||
|
||||
// execute program
|
||||
this->step();
|
||||
|
||||
|
||||
// wait 5 cycles to flush the pipeline
|
||||
this->wait(5);
|
||||
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
52
hw/unit_tests/cache/simulator.h
vendored
Normal file
52
hw/unit_tests/cache/simulator.h
vendored
Normal file
@@ -0,0 +1,52 @@
|
||||
#pragma once
|
||||
|
||||
#include "VVX_priority_encoder.h"
|
||||
#include "VVX_priority_encoder__Syms.h"
|
||||
#include "verilated.h"
|
||||
|
||||
#ifdef VCD_OUTPUT
|
||||
#include <verilated_vcd_c.h>
|
||||
#endif
|
||||
|
||||
//#include <VX_config.h>
|
||||
|
||||
#include <ostream>
|
||||
#include <vector>
|
||||
|
||||
class Simulator {
|
||||
public:
|
||||
|
||||
Simulator();
|
||||
virtual ~Simulator();
|
||||
|
||||
void load_bin(const char* program_file);
|
||||
void load_ihex(const char* program_file);
|
||||
|
||||
bool is_busy();
|
||||
|
||||
void reset();
|
||||
void step();
|
||||
void wait(uint32_t cycles);
|
||||
void flush_caches(uint32_t mem_addr, uint32_t size);
|
||||
|
||||
|
||||
bool run();
|
||||
void print_stats(std::ostream& out);
|
||||
|
||||
private:
|
||||
|
||||
void eval();
|
||||
|
||||
void eval_dram_bus();
|
||||
void eval_io_bus();
|
||||
void eval_snp_bus();
|
||||
|
||||
uint32_t snp_req_active_;
|
||||
uint32_t snp_req_size_;
|
||||
uint32_t pending_snp_reqs_;
|
||||
|
||||
VVX_priority_encoder *vortex_;
|
||||
#ifdef VCD_OUTPUT
|
||||
VerilatedVcdC *trace_;
|
||||
#endif
|
||||
};
|
||||
59
hw/unit_tests/cache/testbase.cpp
vendored
Normal file
59
hw/unit_tests/cache/testbase.cpp
vendored
Normal file
@@ -0,0 +1,59 @@
|
||||
#include "VVX_generic_queue.h"
|
||||
#include "VVX_generic_queue__Syms.h"
|
||||
#include "verilated.h"
|
||||
|
||||
#include <verilated_vcd_c.h>
|
||||
|
||||
#include <iostream>
|
||||
#include <vector>
|
||||
|
||||
uint64_t timestamp = 0;
|
||||
|
||||
double sc_time_stamp() {
|
||||
return timestamp;
|
||||
}
|
||||
|
||||
int main(int argc, char **argv){
|
||||
Verilated::commandArgs(argc, argv); //passes the command args to the object
|
||||
|
||||
VVX_generic_queue *tb = new VVX_generic_queue;
|
||||
tb->reset = 1;
|
||||
tb->eval();
|
||||
tb->reset = 0;
|
||||
unsigned int clk;
|
||||
bool full;
|
||||
bool empty;
|
||||
int size;
|
||||
int data_out;
|
||||
tb->data_in = 0xff;
|
||||
|
||||
tb->push = 1;
|
||||
|
||||
for (int i = 0; i < 5; ++i){
|
||||
//toggle the clock
|
||||
tb->eval();
|
||||
tb->clk = 1;
|
||||
|
||||
tb->eval();
|
||||
tb->clk = 0;
|
||||
tb->eval();
|
||||
|
||||
|
||||
full = tb->full;
|
||||
empty = tb->empty;
|
||||
size = tb->size;
|
||||
data_out = tb->data_out;
|
||||
clk = tb->clk;
|
||||
|
||||
std::cout << "clk: " << clk << std::endl;
|
||||
std::cout << "data_out: " << data_out << std::endl;
|
||||
std::cout << "empty: " << empty << std::endl;
|
||||
std::cout << "full: " << full << std::endl;
|
||||
std::cout << "size: " << size << std::endl;
|
||||
|
||||
}
|
||||
|
||||
delete tb;
|
||||
|
||||
exit(0);
|
||||
}
|
||||
12
hw/unit_tests/cache/testbench.cpp
vendored
Normal file
12
hw/unit_tests/cache/testbench.cpp
vendored
Normal file
@@ -0,0 +1,12 @@
|
||||
#include "simulator.h"
|
||||
#include <iostream>
|
||||
#include <fstream>
|
||||
#include <iomanip>
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
Simulator simulator;
|
||||
bool curr = simulator.run();
|
||||
|
||||
return 0;
|
||||
}
|
||||
Reference in New Issue
Block a user