Using verilog For-loops + Passing all tests

2019-03-30 22:09:03 -04:00
parent 99a0792a0c
commit a3a3b21de7
17 changed files with 1204 additions and 984 deletions
--- a/rtl/test_bench.cpp
+++ b/rtl/test_bench.cpp
@@ -78,7 +78,7 @@ int main(int argc, char **argv)
 		if(!passed) std::cerr << DEFAULT << "Failed one or more tests\n";


-	// char testing[] = "../../emulator/riscv_tests/rv32ui-p-lw.hex";
+	// char testing[] = "../../emulator/riscv_tests/rv32ui-p-sw.hex";

 	// bool curr = v.simulate(testing);
 	// if ( curr) std::cerr << GREEN << "Test Passed: " << testing << std::endl;